133 Commits

Author SHA1 Message Date
Ben Shi
cb45be2b4f [RISCV][NFC] Combine identical switch cases in TTI
Reviewed By: craig.topper, asb

Differential Revision: https://reviews.llvm.org/D146008
2023-03-15 08:27:58 +08:00
Luke Lau
a9d9616c0d [RISCV][NFC] Share interleave mask checking logic
This adds two new methods to ShuffleVectorInst, isInterleave and
isInterleaveMask, so that the logic to check if a shuffle mask is an
interleave can be shared across the TTI, codegen and the interleaved
access pass.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D145971
2023-03-14 11:02:52 +00:00
Philip Reames
ca0cd670dc [RISCV] Improve SK_Reverse shuffle costs for fixed length vectors
As noted by @luke (https://reviews.llvm.org/D145953#inline-1409312), we were accounting for the cost of vector element size using vlenb whereas the expression can be constant folded for fixed length vectors.

Differential Revision: https://reviews.llvm.org/D145973
2023-03-13 15:17:42 -07:00
Philip Reames
64fc41ad82 [RISCV] Extend SK_Broadcast costing to scalable vectors
The existing scalable costing was just bad.  No LMUL cost, no i1 specific costing, etc..  We had updated the fixed cost model, but none of the code is actually fixed length specific.  Moving it down handles the scalable cases too.
2023-03-13 11:07:26 -07:00
Philip Reames
a37dfbb79c [RISCV] Fallback to scalable lowering costs for fixed length vectors
Fixed vector costs may be more precise, but the actual lowering will use scalable vectors if nothing better is available.  During review, we noticed a case where fixed vector reverse can be improved cost model wise, that will follow seperately.

Differential Revision: https://reviews.llvm.org/D145953
2023-03-13 10:07:57 -07:00
Philip Reames
cfcf274245 [RISCV] Inline and delete RISCVTTIImpl::getSpliceCost [nfc]
The code structure was copied from AArch64 which has a much more complicated splice cost model.
2023-03-13 08:55:32 -07:00
Philip Reames
21bca796d7 [RISCV] Use switch in RISCVTargetTransformInfo::getShuffleCost [nfc]
Refactoring in advance of a semantic change.
2023-03-13 08:40:47 -07:00
Luke Lau
c417266db5 [RISCV] Model interleave and deinterleave shuffles in cost model
Interleave and deinterleave shuffles are lowered by a more efficient
sequence if the element size is smaller than ELEN.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D145678
2023-03-10 01:10:00 +00:00
ShihPo Hung
fb661e2554 [CostModel][RISCV] Model code size cost for reduction
Since code-size cost doesn't scale linearly with LMUL,
this change is to separate it from throughput.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D142068
2023-03-05 17:58:45 -08:00
Kazu Hirata
a28b252d85 Use APInt::getSignificantBits instead of APInt::getMinSignedBits (NFC)
Note that getMinSignedBits has been soft-deprecated in favor of
getSignificantBits.
2023-02-19 23:56:52 -08:00
Kazu Hirata
e078201835 [Target] Use llvm::count{l,r}_{zero,one} (NFC) 2023-01-28 09:23:07 -08:00
Kazu Hirata
7a3e87298e [RISCV] Use llvm::bit_floor and std::clamp (NFC) 2023-01-28 00:49:38 -08:00
Philip Reames
a9871772a8 [RISCV][LSR] Treat number of instructions as dominate factor in LSR cost decisions
This matches the behavior from a number of other targets, including e.g. X86. This does have the effect of increasing register pressure slightly, but we have a relative abundance of registers in the ISA compared to other targets which use the same heuristic.

The motivation here is that our current cost heuristic treats number of registers as the dominant cost. As a result, an extra use outside of a loop can radically change the LSR result. As an example consider test4 from the recently added test/Transforms/LoopStrengthReduce/RISCV/lsr-cost-compare.ll. Without a use outside the loop (see test3), we convert the IV into a pointer increment. With one, we leave the gep in place.

The pointer increment version both decreases number of instructions in some loops, and creates parallel chains of computation (i.e. decreases critical path depth). Both are generally profitable.

Arguably, we should really be using a more sophisticated model here - such as e.g. using profile information or explicitly modeling parallelism gains. However, as a practical matter starting with the same mild hack that other targets have used seems reasonable.

Differential Revision: https://reviews.llvm.org/D142227
2023-01-24 11:42:37 -08:00
ShihPo Hung
5fb3a57ea7 [Cost] Add CostKind to getVectorInstrCost and its related users
LoopUnroll estimates the loop size via getInstructionCost(),
but getInstructionCost() cannot pass CostKind to getVectorInstrCost().
And so does getShuffleCost() to getBroadcastShuffleOverhead(),
getPermuteShuffleOverhead(), getExtractSubvectorOverhead(),
and getInsertSubvectorOverhead().

To address this, this patch adds an argument CostKind to these
functions.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D142116
2023-01-21 05:29:24 -08:00
liqinweng
1f8746cc80 [RISCV][CostModel] Add half type support for the cost model of sqrt/fabs
1. Refactor for costs of sqrt/fabs
2. Add half type support for the cost model of sqrt/fabs

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D132908
2023-01-09 12:57:03 +08:00
liqinweng
f3408739da [RISCV][CostModel] Add cost model for integer abs
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D132999
2023-01-09 11:38:24 +08:00
Alexey Bataev
9b5f62685a [SLP]Fix cost of the broadcast buildvector/gather.
Need to include the cost of the initial insertelement to the cost of the
broadcasts. Also, need to adjust the cost of the gather/buildvector if
the element is inserted into poison/undef vector.

Differential Revision: https://reviews.llvm.org/D140498
2023-01-06 09:25:05 -08:00
Guillaume Chatelet
87b6b347fc Revert D141134 "[NFC] Only expose getXXXSize functions in TypeSize"
The patch should be discussed further.

This reverts commit dd56e1c92b0e6e6be249f2d2dd40894e0417223f.
2023-01-06 15:27:50 +00:00
Guillaume Chatelet
dd56e1c92b [NFC] Only expose getXXXSize functions in TypeSize
Currently 'TypeSize' exposes two functions that serve the same purpose:
 - getFixedSize / getFixedValue
 - getKnownMinSize / getKnownMinValue

source : bf82070ea4/llvm/include/llvm/Support/TypeSize.h (L337-L338)

This patch offers to remove one of the two and stick to a single function in the code base.

Differential Revision: https://reviews.llvm.org/D141134
2023-01-06 15:24:52 +00:00
Craig Topper
239a174d92 [RISCV] Prevent constant hoisting for or/and/xor that can use bseti/bclri/binvi.
Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D140928
2023-01-05 11:18:31 -08:00
Yeting Kuo
1e9e1b9cf8 [VP][RISCV] Add vp.ctlz/cttz and RISC-V support.
The patch also adds expandVPCTLZ and expandVPCTTZ to expand vp.ctlz/cttz nodes
and the cost model of vp.ctlz/cttz.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140370
2023-01-04 15:15:01 +08:00
Yeting Kuo
ad68586a37 [VP][RISCV] Add vp.ctpop and RISC-V support.
The patch also adds expandVPCTPOP in TargetLowering to expand VP_CTPOP nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139920
2022-12-14 09:47:44 +08:00
Yeting Kuo
47b9da72e0 [VP][RISCV] Add vp.bitreverse and RISC-V support.
The patch also added function expandVPBITREVERSE to expand ISD::VP_BITREVERSE nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139697
2022-12-12 10:58:44 +08:00
Yeting Kuo
0f8c761c48 [VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support."
This reverts commit 7883e5b061bdbbe8bee5f479ebe911db5045b7e9.

The original commit was reverted that it didn't update test files after D136263
landed. The recommit fixed those.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139509
2022-12-07 15:58:12 +08:00
Kazu Hirata
7883e5b061 Revert "[VP][RISCV] Add vp.fshl/fshr and RISC-V support."
This reverts commit 70de0e014013b4d97febe6704881a9a8c893d078.

I'm seeing:

Failed Tests (2):
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fshr-fshl-vp.ll

Also reported at:

https://lab.llvm.org/buildbot/#/builders/123/builds/14531
2022-12-06 22:27:43 -08:00
Yeting Kuo
8c8a6e1488 [RISCV] Add basic cost model for vp float rounding instructions.
Reviewed By: craig.topper, reames

Differential Revision: https://reviews.llvm.org/D137766
2022-12-07 14:15:13 +08:00
Yeting Kuo
70de0e0140 [VP][RISCV] Add vp.fshl/fshr and RISC-V support.
The patch made VectorLegalizer expand ISD::VP_FSHL and ISD::VP_FSHR to
achieve the codegen.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D138379
2022-12-07 12:16:36 +08:00
Krzysztof Parzyszek
86fe4dfdb6 TargetTransformInfo: convert Optional to std::optional
Recommit: added missing "#include <cstdint>".
2022-12-02 11:42:15 -08:00
Krzysztof Parzyszek
4e12d1836a Revert "TargetTransformInfo: convert Optional to std::optional"
This reverts commit b83711248cb12639e7ef7303cfbb4452b4067e85.

Some buildbots are failing.
2022-12-02 11:34:04 -08:00
Krzysztof Parzyszek
b83711248c TargetTransformInfo: convert Optional to std::optional 2022-12-02 11:27:12 -08:00
Krzysztof Parzyszek
26424c96c0 Attributes: convert Optional to std::optional 2022-12-02 08:15:45 -06:00
Philip Reames
73eacf94e0 [RISCV] Incorporate LMUL into costs for arithmetic and shuffles
This reuses the routine implemented in 0e6f0b7 to implement several existing TODOs. Many of the operations scale linearly with LMUL; this change represents that in the cost model.

Differential Revision: https://reviews.llvm.org/D139039
2022-12-01 10:46:27 -08:00
Philip Reames
7d82c99403 [RISCV][TTI] Account for constant materialization cost when costing arithmetic operations
At the IR level, we generally assume that constants are free to materialize. However, for RISCV due to some quirks of the ISA, materializing arbitrary constants can be rather expensive. We frequently fallback to constant pool loads.

We've been slowly moving in the direction of modeling the cost of the remat as part of the instruction cost. This has the effect of disincentivizing vectorization - mostly SLP - when we'd have to materialize an expensive constant.

We need better modeling of which constants are expensive and not, but the moment let's be consistent with how we model arithmetic and memory instructions. The difference between the two is that arithmetic can sometimes fold a splat operation which stores can not.

Differential Revision: https://reviews.llvm.org/D138941
2022-11-30 07:20:51 -08:00
ShihPo Hung
0e6f0b7cc3 [RISCV] Add cost model for fixed broadcast shuffle
This patch adds basic broadcast shuffle costs in order to enable SLP vectorization.
And adds `getLMULCost` to consider reciprocal throughput for different LMUL.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D137276
2022-11-30 04:58:52 -08:00
Philip Reames
db07d79ab0 [RISCV] Add cost model for integer and float vector arithmetic instructions.
This patch implements getArithmeticInstrCost for RISCV, supports cost
model for integer and float vector arithmetic instructions.

Differential Revision: https://reviews.llvm.org/D133552 (Original patch by jacquesguan.  Subset by me with todos added.)
2022-11-28 09:04:38 -08:00
Philip Reames
d2cf0bd78d [RISCV] Add callback plumbing for getArithmeticInstrCost [nfc]
Most of the code for this was taken from https://reviews.llvm.org/D133552, with one bug fix by me.  I'm landing the plumbing so that we can focus on the cost model pieces in the review.
2022-11-22 18:53:23 -08:00
Craig Topper
a391b49ce8 [RISCV] Prevent constant hoisting for (and (shl X, C), mask<<C)
If the immediate is a shifted mask, we will use a pair of shifts
and never materialize the immediate. Consider the immediate free.

Reviewed By: reames, luismarques

Differential Revision: https://reviews.llvm.org/D138260
2022-11-21 19:16:40 -08:00
Yeting Kuo
ed9638c44b [VP][RISCV] Add vp.nearbyint and RISC-V support.
nearbyint has the property to execute without exception.
For not modifying fflags, the patch added new machine opcode
PseudoVFROUND_NOEXCEPT_V that expands vfcvt.x.f.v and vfcvt.f.x.v between a pair
of frflags and fsflags.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D137685
2022-11-16 14:05:35 +08:00
Yeting Kuo
5c3ca10b09 [VP][RISCV] Add vp.bswap and RISC-V support.
The patch also added function expandVPBSWAP to expand ISD::VP_BSWAP nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D137928
2022-11-16 11:36:38 +08:00
Craig Topper
b6ad7ab89e [RISCV] Prevent autovectorization using vscale with Zvl32b.
RVVBitsPerBlock is 64. If VLen==32, VLen/RVVBitsPerBlock is 0.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D137280
2022-11-02 13:55:21 -07:00
Philip Reames
73482b457e [RISCV] Fix cost of legal fixed length masked load and stores
We can cost them the same way as a scalable masked load/store. By hitting the default path, we were costing them as if they were being scalarized. This is a significant over estimate.

Differential Revision: https://reviews.llvm.org/D137218
2022-11-02 07:24:38 -07:00
Yeting Kuo
71e4e35581 [VP][RISCV] Add vp.rint and RISC-V support.
FRINT uses dynamic rounding mode instead of static rounding mode. The patch
rename VFCVT_X_F_VL to VFCVT_RM_X_F_VL for static rounding mode uses and added
new ISDNode VFCVT_X_F_VL directly selected to PseudoVFCVT_X_F_V.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D136662
2022-11-01 14:52:47 +08:00
Craig Topper
e94dc58dff [RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
This avoids the call overhead as well as the the save/restore of
fflags and the snan handling in the libm function.

The save/restore of fflags and snan handling are needed to be
correct for -ftrapping-math. I think we can ignore them in the
default environment.

The inline sequence will generate an invalid exception for nan
and an inexact exception if fractional bits are discarded.

I've used a custom inserter to explicitly create the control flow
around the float->int->float conversion.

We can probably avoid the final fsgnj after the conversion for
no signed zeros FMF, but I'll leave that for future work.

Note the comparison constant is slightly different than glibc uses.
They use 1<<53 for double, I'm using 1<<52. I believe either are valid.
Numbers >= 1<<52 can't have any fractional bits. It's ok to do the
float->int->float conversion on numbers between 1<<53 and 1<<52 since
they will all fit in 64. We only have a problem if the double can't fit
in i64

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136508
2022-10-26 14:36:49 -07:00
Craig Topper
d4dc036e70 [RISCV] Move vector cost table lookup out of the switch in getIntrinsicInstrCost. NFC
This allows vectors to be looked up if the switch is used for the
scalar version of an intrinsic.

Extracted from D136508.
2022-10-24 20:32:22 -07:00
Craig Topper
020450211b [RISCV] Add missing vscale x 1 cost model entries and tests.
Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136411
2022-10-21 09:05:59 -07:00
Craig Topper
44f0b13494 [RISCV] Correct RISCVTTIImpl::getRegUsageForType for vectors of pointers.
getPrimitiveSizeInBits returns 0 for pointers, we need to query
the size via DataLayout instead.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D135976
2022-10-14 11:34:12 -07:00
Craig Topper
de0de294eb [RISCV] Update cost of vector roundeven to match round which uses the same sequence but a different FRM value.
Reviewed By: reames, eopXD

Differential Revision: https://reviews.llvm.org/D134978
2022-09-30 20:01:35 -07:00
Philip Reames
02bfe2de7c [RISCV] Adjust vector immediate store materialization cost
This change updates the costs to make constant pool loads match their actual cost, and adds the broadcast special case to avoid too many regressions. We really need more information about the constants being rematerialized, but this is an incremental improvement.

Differential Revision: https://reviews.llvm.org/D134746
2022-09-29 07:37:13 -07:00
Philip Reames
77b202f974 [RISCV] Rename getVectorImmCost to getStoreImmCost [nfc]
My original intent had been to reuse this for arithmetic instructions as well, but due to the availability of a immediate splat encoding there, we will need different heuristics.  So specialize the existing code for the store case.
2022-09-27 08:22:13 -07:00
jacquesguan
ecf327f154 [RISCV] Add cost model for vector insert/extract element.
This patch adds cost model for vector insert/extract element instructions. In RVV, we could use vector scalar move instruction to insert or extract the first element, and use vslide to move it. But for mask vector or i64 vector in i32 target, we need special instructions to make it.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D133007
2022-09-14 11:10:18 +08:00