4 Commits

Author SHA1 Message Date
David Green
1c6ea96193 [AArch64] Fix load-insert-zero patterns with i8 and negative offsets.
These should have been using the LDURBi instructions where the offset is
negative, as reported from the reproducer in D144086.
2023-03-08 12:48:21 +00:00
David Green
a10ac6554d [AArch64] Extend load insert into zero patterns to SVE.
This extends the patterns for loading into the zeroth lane of a zero vector
from D144086 to SVE, which work in the same way as the existing patterns. Only
full length vectors are added here, not the narrower floating point vector
types.
2023-03-06 23:26:08 +00:00
David Green
83bbd3fdbd [AArch64] Load into zero vector patterns
A LDR will implicitly zero the rest of the vector, so vector_insert(zeros,
load, 0) can use a single load. This adds tablegen patterns for both scaled and
unscaled loads, detecting where we are inserting a load into the lower element
of a zero vector.

Differential Revision: https://reviews.llvm.org/D144086
2023-03-01 13:54:03 +00:00
David Green
afa557fad6 [AArch64] Add a test for loading into a zerovector. NFC 2023-02-21 14:42:53 +00:00