232 Commits

Author SHA1 Message Date
Evan Cheng
6ad7da96fe - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745
2009-11-14 02:55:43 +00:00
Evan Cheng
95bdc5d899 RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg,
and extract_subreg as a "copy" that defines a valno.
Also fixes a typo. These two issues prevent a simple subreg coalescing from
happening before.

llvm-svn: 86022
2009-11-04 08:33:14 +00:00
Lang Hames
05fb9637f6 The Indexes Patch.
This introduces a new pass, SlotIndexes, which is responsible for numbering
instructions for register allocation (and other clients). SlotIndexes numbering
is designed to match the existing scheme, so this patch should not cause any
changes in the generated code.

For consistency, and to avoid naming confusion, LiveIndex has been renamed
SlotIndex.

The processImplicitDefs method of the LiveIntervals analysis has been moved
into its own pass so that it can be run prior to SlotIndexes. This was
necessary to match the existing numbering scheme.

llvm-svn: 85979
2009-11-03 23:52:08 +00:00
Lang Hames
94966ca926 Stop the iterator in ValueLiveAt from potentially running off the end of the interval.
llvm-svn: 85599
2009-10-30 18:12:09 +00:00
Bill Wendling
c44768ae69 Reapply r85338.
llvm-svn: 85514
2009-10-29 17:39:46 +00:00
Bill Wendling
a8eceedb82 Reverting r85338 for now. It's causing a bootstrap failure on PPC darwin9.
--- Reverse-merging r85338 into '.':
U    lib/CodeGen/SimpleRegisterCoalescing.cpp
U    lib/CodeGen/SimpleRegisterCoalescing.h

llvm-svn: 85454
2009-10-29 00:22:16 +00:00
Lang Hames
cd3939ef0e Fixed a bug in the coalescer where intervals were occasionally merged despite a real interference. This fixes rdar://problem/7157961.
llvm-svn: 85338
2009-10-27 23:16:58 +00:00
Evan Cheng
b81cb2a9a8 - Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests and
bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
  around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
  common for targets to operate on registers where the top bits are undef. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
     = d0
  When the insert_subreg is eliminated by the coalescer, the scavenger used to
  complain. The previous fix was to keep to insert_subreg around. But that's
  brittle and it's overly conservative when we want to use the scavenger to 
  allocate registers. It's actually legal and desirable for other instructions
  to use the "undef" part of d0. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
  s1 =
     = s1
     = d0
  We probably need add a "partial-undef" marker on machine operand so the
  machine verifier would not complain.

llvm-svn: 85091
2009-10-26 04:56:07 +00:00
Evan Cheng
19348415c4 Do not delete identity insert_subreg even if dest is virtual. Let later passes delete them. This avoids register scavenger complain.
llvm-svn: 85045
2009-10-25 07:48:51 +00:00
Dan Gohman
8f4078ba39 Rename isLoopExit to isLoopExiting, for consistency with the wording
used elsewhere - an exit block is a block outside the loop branched to
from within the loop. An exiting block is a block inside the loop that
branches out.

llvm-svn: 85019
2009-10-24 23:34:26 +00:00
Evan Cheng
d638bc310a Identity copies should not contribute to spill weight.
llvm-svn: 84978
2009-10-23 23:09:19 +00:00
Dan Gohman
87b02d5bbc Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.

llvm-svn: 83687
2009-10-09 23:27:56 +00:00
Dan Gohman
e19c1810d7 isTriviallyReMaterializable checks the
TargetInstrDesc::isRematerializable flag, so it isn't necessary to do
this check in its callers.

llvm-svn: 83671
2009-10-09 21:02:10 +00:00
Lang Hames
a7780905e7 Oops. Renamed remaining MachineInstrIndex references.
llvm-svn: 83255
2009-10-03 04:31:31 +00:00
Lang Hames
920301ecc5 Renamed MachineInstrIndex to LiveIndex.
llvm-svn: 83254
2009-10-03 04:21:37 +00:00
Evan Cheng
e0c5313493 Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of
physical registers. This is especially critical for the later two since they
start the live interval of a super-register. e.g.
%DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
If this instruction is eliminated, the register scavenger will not be happy as
D0 is not defined previously.
This fixes PR5055.

llvm-svn: 82968
2009-09-28 05:28:43 +00:00
Evan Cheng
a21aac3811 Clean up LiveVariables and change how it deals with partial updates and kills. This also eliminate the horrible check which scan forward to the end of the basic block. It should be faster and more accurate.
llvm-svn: 82676
2009-09-24 02:15:22 +00:00
Evan Cheng
b2abe07457 Fix a obvious logic error.
llvm-svn: 82610
2009-09-23 05:23:19 +00:00
Evan Cheng
0dfed43a5b Fix a pasto. Also simplify for Bill's benefit.
llvm-svn: 82505
2009-09-22 01:48:19 +00:00
Evan Cheng
255f416470 Clean up spill weight computation. Also some changes to give loop induction
variable increment / decrement slighter high priority. 

This has major impact on some micro-benchmarks. On MultiSource/Applications
and spec tests, it's a minor win. It also reduce 256.bzip instruction count
by 8%, 55 on 164.gzip on i386 / Darwin.

llvm-svn: 82485
2009-09-21 21:12:25 +00:00
Dan Gohman
a3c45bda22 Fix this assertion string to mention subreg_to_reg.
llvm-svn: 82455
2009-09-21 15:18:33 +00:00
Daniel Dunbar
7d6781b0fe Tabs -> spaces, and remove trailing whitespace.
llvm-svn: 82355
2009-09-20 02:20:51 +00:00
Evan Cheng
f56b0482c4 Fix PR4910: Broken logic in coalescer means when a physical register liveness is being shortened, the sub-registers were not. The symptom is the register allocator could not find a free register for this particular test.
llvm-svn: 82108
2009-09-17 00:57:15 +00:00
Evan Cheng
760c92a5be Remove -new-coalescer-heuristic. It's not useful.
llvm-svn: 81600
2009-09-12 02:14:41 +00:00
Evan Cheng
a7afdda65d When remat'ing and destination virtual register has a sub-register index. Make sure the sub-register class matches the register class of the remat'ed instruction definition register class.
llvm-svn: 81204
2009-09-08 06:39:07 +00:00
Lang Hames
3fffe62177 Replaces uses of unsigned for indexes in LiveInterval and VNInfo with
a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.

llvm-svn: 81040
2009-09-04 20:41:11 +00:00
Chris Lattner
471ba48cb9 remove some uses of llvm/Support/Streams.h
llvm-svn: 79842
2009-08-23 08:43:55 +00:00
Chris Lattner
1362602eb2 Change Pass::print to take a raw ostream instead of std::ostream,
update all code that this affects.

llvm-svn: 79830
2009-08-23 06:03:38 +00:00
Bill Wendling
058687e360 Convert DOUT to DEBUG(errs()...).
llvm-svn: 79765
2009-08-22 20:52:46 +00:00
Lang Hames
3b90d973b0 Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg.
llvm-svn: 78620
2009-08-10 23:43:28 +00:00
Evan Cheng
b1aeeed03e Another coalescer bug. When a dead copy is eliminated, transfer the kill to a def of the exact register rather than a super-register.
llvm-svn: 78376
2009-08-07 07:14:14 +00:00
Benjamin Kramer
d06eaca66f Rename a variable to make MSVC happy.
llvm-svn: 78202
2009-08-05 16:08:58 +00:00
Evan Cheng
a2ce665f60 Another nasty coalescer bug (is there another kind):
After coalescing reg1027's def and kill are both at the same point:
 %reg1027,0.000000e+00 = [56,814:0)  0@70-(814)

bb5:
60   %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
68   %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
76   t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
84   %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
96   t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>

Do not remove the kill marker on t2LDRi12.

llvm-svn: 78178
2009-08-05 07:05:41 +00:00
Evan Cheng
093e124256 Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy.
llvm-svn: 77967
2009-08-03 08:41:59 +00:00
Dan Gohman
0402315d41 Use setPreservesAll and setPreservesCFG in CodeGen passes.
llvm-svn: 77754
2009-07-31 23:37:33 +00:00
Chris Lattner
7667332899 inline the global 'getInstrOperandRegClass' function into its callers
now that TargetOperandInfo does the heavy lifting.

llvm-svn: 77508
2009-07-29 21:36:49 +00:00
Mike Stump
d934cc06c6 Avoid build warnings.
llvm-svn: 77271
2009-07-27 23:14:11 +00:00
Daniel Dunbar
0dd5e1ed39 More migration to raw_ostream, the water has dried up around the iostream hole.
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.

llvm-svn: 77019
2009-07-25 00:23:56 +00:00
David Greene
1e2a04ba99 Make some changes suggested by Bill and Evan.
llvm-svn: 76775
2009-07-22 20:08:25 +00:00
David Greene
3424275325 Add some support for iterative coalescers to calculate a joined live
range's weight properly.  This is turned off right now in the sense that
you'll get an assert if you get into a situation that can only be caused
by an iterative coalescer.  All other code paths operate exactly as
before so there is no functional change with this patch.  The asserts
should be disabled if/when an iterative coalescer gets added to trunk.

llvm-svn: 76680
2009-07-21 23:36:14 +00:00
Evan Cheng
9a47392f2e Cross RC coalescing is now on by default.
llvm-svn: 76519
2009-07-21 00:22:59 +00:00
Evan Cheng
027d9f93ea Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class.
llvm-svn: 76458
2009-07-20 19:47:55 +00:00
Evan Cheng
090db9b7a9 Catch more coalescing opportunities.
llvm-svn: 76282
2009-07-18 04:52:23 +00:00
Evan Cheng
e20cbf3068 Enable cross register class coalescing.
llvm-svn: 76281
2009-07-18 02:10:10 +00:00
Evan Cheng
97b9a4b412 Simplify some more.
llvm-svn: 76239
2009-07-17 21:06:58 +00:00
Evan Cheng
f08b003bf0 Simplify the coalescer (finally!) by making LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands.
llvm-svn: 76223
2009-07-17 19:43:40 +00:00
Evan Cheng
84517443ca Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900
2009-07-16 09:20:10 +00:00
Evan Cheng
43229fb489 ShortenDeadCopySrcLiveRange needs to be more conservative in multi-kill situations.
llvm-svn: 75838
2009-07-15 21:39:50 +00:00
Torok Edwin
fbcc663cbf llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Evan Cheng
26bed68f5b Fix pr4544. When remating, make sure the destination register fits the instruction definition. It may be mismatched due to sub-register coalescing.
No test case yet because the code doesn't trigger until 75408 is re-applied.

llvm-svn: 75572
2009-07-14 00:51:06 +00:00