These concepts don't exist for MCRegister.
I think there is a need for virtual registers in MCRegister for NVPTX,
SPIR-V and WebAssembly, but those should not be confused with Register's
virtual register. I will try to make a separate proposal for that with a
real interface.
setType is unneeded (and AsmPrinter tries not to modify symbols).
AsmPrinter. MCSA_ELF_TypeFunction is available on all
targets using getSymbolPreferLocal.
Pull Request: https://github.com/llvm/llvm-project/pull/128138
Check that the input register is an inreg argument to the parent
function. (See the comment in `IntrinsicsAMDGPU.td`.)
This LLVM defect was identified via the AMD Fuzzing project.
---------
Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
They were instantiated with only a single type and union-members
themselves. By putting the types directly into a union, they are still
left uninitialized by default.
While processing library link options that check search paths (-lx, -hidden-lx,
etc.) we shouldn't generate candidate paths with extensions that are invalid
for the option being visited (e.g. -hidden-lx only applies to archives, so we
shouldn't generate candidates with `.so` extensions).
Note: Candidate extensions should probably be further filtered based on the OS
of the executing process. This patch is a step in the right direction though.
Remove the MIR scan to detect whether AGPRs are used or not,
and the special case for callable functions. This behavior was
confusing, and not overridable. The amdgpu-no-agpr attribute was
intended to avoid this imprecise heuristic for how many AGPRs to
allocate. It was also too confusing to make this interact with
the pending amdgpu-num-agpr replacement for amdgpu-no-agpr.
Also adds an xfail-ish test where the register allocator asserts
after allocation fails which I ran into.
Future work should reintroduce a more refined MIR scan to estimate
AGPR pressure for how to split AGPRs and VGPRs.
Noticed some oddities in the InversePseudo table. TIED pseudos are
in there but sorted differently than their non-TIED version. I think
we always check non-zero SEW first which should hit the non-tied version.
I'm working on a larger patch to remove _MASK and _TIED from the
InversePseudo table.
This removes "replaceFunctionWithNamedStructOp" and folds its
functionality into "replaceFunctionWithOp". It turns out we were
overcomplicating things and this is trivial to handle generically.
Fixes#113192
SETULT can be an unsigned less than integer compare or a unordered less
than FP compare. We need to check the VT to distinguish them.
Fixes on of the issues from #128237.
When using multi-config generator to build `libLLVM.so` like `cmake -G
'Ninja Multi-Config' -Sllvm -B/tmp/out/ninja-multi
-DCMAKE_CONFIGURATION_TYPES='Debug;Release' -DLLVM_LINK_LLVM_DYLIB=on
-DLLVM_TARGETS_TO_BUILD=host && cmake --build /tmp/out/ninja-multi
--config Debug`, `lld` complains `error: cannot find version script
/tmp/out/ninja-multi/Debug/lib/tools/llvm-shlib/simple_version_script.map`.
This patch adds multi-config compatibility when configuring
`simple_version_script.map`.
Fixes#63800.
When using multi-config generator, clang's headers is not copied to
proper directories, which is fixed as well.
Update HCFG builder to set the incoming values directly at construction
for non-header phis.
Simplification/clarification as suggested independently in
https://github.com/llvm/llvm-project/pull/126388.
Remove the restriction when reusing wider BROADCAST_LOAD nodes that both nodes couldn't have uses of their load chains - use makeEquivalentMemoryOrdering to merge the chains instead.
To simplify debugging and analysis, particularly for very large
applications with large graphs, this patch adds support for either
highlighting a single context id or allocation's context ids, and/or
only exporting the nodes/edges for a single context id or allocation's
context ids. When highlighting, the specified nodes and edges are a
brighter color and larger.
This can be controlled by the new -memprof-dot-scope={all,alloc,context}
flag which controls how much to export, along with two companion flags:
-memprof-dot-alloc-id=ID
-memprof-dot-context-id=ID
These two are interpreted differently depending on the value of
-memprof-dot-scope (where "all" is the default).
If exporting all, one of the above flags can optionally be passed to
highlight the nodes/edges for the given context id or allocation's
context ids.
If exporting alloc scope, an alloc id must be provided. A context id can
optionally be provided to highlight that context.
If exporting context scope, a context id must be provided.
The ids to use can be obtained either by looking at the full graph, or a
context id can be identified from the -memprof-report-hinted-sizes
output after PR128188 is merged.
During the whole program reporting of contexts when hinted byte
reporting is enabled via -memprof-report-hinted-sizes, also print the
internal context id. This is useful for debugging, as well as for
guiding the dot file dumping with some upcoming changes that will
accept a context id to focus the graph on a context of interest.
This is a copy of #126177, since it was automatically and permanently
closed because I messed up the source branch on my remote
This patch proposes to avoid converting widening recipes to VP
intrinsics during the EVL transform.
IIUC we initially did this to avoid `vl` toggles on RISC-V. However we
now have the RISCVVLOptimizer pass which mostly makes this redundant.
Emitting regular IR instead of VP intrinsics allows more generic
optimisations, both in the middle end and DAGCombiner, and we generally
have better patterns in the RISC-V backend for non-VP nodes. Sticking to
regular IR instructions is likely a lot less work than reimplementing
all of these optimisations for VP intrinsics, and on SPEC CPU 2017 we get
noticeably better code generation.
Replace binary of of two reductions with one reduction of the binary op
applied to vectors. For example:
```
%v0_red = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v0)
%v1_red = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v1)
%res = add i32 %v0_red, %v1_red
```
gets transformed to:
```
%1 = add <16 x i32> %v0, %v1
%res = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %1)
```
