19 Commits

Author SHA1 Message Date
Qinkun Bao
1b0f139f8e
Revert "[NFC][LiveStacks] Use vectors instead of map and unordred_map" (#180421)
Reverts llvm/llvm-project#165477

Break https://lab.llvm.org/buildbot/#/builders/52/builds/14874
2026-02-08 16:54:51 +00:00
Ralender
1acc200d88
[NFC][LiveStacks] Use vectors instead of map and unordred_map (#165477) 2026-02-07 15:31:43 +00:00
Rahul Joshi
295eba2058
[NFC][AMDGPU] Remove pass initialization from pass constructors (#180149) 2026-02-06 09:05:14 -08:00
hjagasiaAMD
2183846a15
[AMDGPU] Fix AGPR_32 reg assign for mfma scale ops (#168964)
In MFMA rewrite pass, prevent AGPR_32 reg class assignment for scale
operands, not permitted by instruction format.

---------

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
2025-12-02 13:41:16 -05:00
Prasoon Mishra
8a3891cead
[AMDGPU][NPM] Preserve analyses in AMDGPURewriteAGPRCopyMFMA for NPM (#170130)
The pass preserved LiveStacksAnalysis but failed to preserve
LiveIntervalsAnalysis, LiveRegMatrixAnalysis, VirtRegMapAnalysis, and
SlotIndexesAnalysis under NPM. This caused these analyses to be
invalidated and recomputed, leading to incorrect behavior in subsequent
passes like VirtRegRewriter.

Fix by explicitly preserving all required analyses in the NPM version,
matching the legacy pass manager behavior.

---------

Co-authored-by: vikhegde <vikram.hegde@amd.com>
2025-12-01 22:56:37 +05:30
weiwei chen
497d648fcc
[AMDGPU] Make sort ordering in AMDGPURewriteAGPRCopyMFMAImpl::eliminateSpillsOfReassignedVGPRs() strict weak. (#162493)
- [x] `sort` needs the comparator with strictly weak ordering, however
current logic doesn't meet the
[**Antisymmetry**](https://tanjim131.github.io/2020-05-22-strict-weak-ordering/#:~:text=Almost%20all%20C++%20STL%20containers,the%20person%20with%20greater%20height.)
requirement with

```
sort 0x561ecd3d3db0,0x561eaba91d10  25
  weight 0.000000e+00,0.000000e+00
  size 650370,662754
  slot 732,733
```

Make the comparator logic strict weak order.

Fixes #162490
2025-10-08 13:05:08 -04:00
Matt Arsenault
babdad3fdb
AMDGPU: Try to unspill VGPRs after rewriting MFMAs to AGPR form (#154323)
After replacing VGPR MFMAs with the AGPR form, we've alleviated VGPR
pressure which may have triggered spills during allocation. Identify
these spill slots, and try to reassign them to newly freed VGPRs,
and replace the spill instructions with copies.

Fixes #154260
2025-09-17 00:11:32 +09:00
Matt Arsenault
da8f692e3e
AMDGPU: Handle V->A MFMA copy from case with immediate src2 (#153023)
Handle a special case for copies from AGPR VGPR on the MFMA inputs.
If the "input" is really a subregister def, we will not see the
usual copy to VGPR for src2, only the read of the subregister def.
Not sure if this pattern appears in practice.
2025-09-03 16:21:46 +09:00
Matt Arsenault
fdede21ddf
AMDGPU: Add statistic for number of MFMAs moved to AGPR form (#153024) 2025-09-03 05:44:25 +00:00
Matt Arsenault
085471d777
AMDGPU: Handle rewriting VGPR MFMA fed from AGPR copy (#153022)
Previously we handled the inverse situation only.
2025-09-03 14:12:45 +09:00
Matt Arsenault
eefad7438c
AMDGPU: Handle rewriting VGPR MFMA to AGPR with subregister copies (#153019)
This should address the case where the result isn't fully used,
resulting in partial copy bundles from the MFMA result.
2025-08-21 01:17:03 +00:00
Matt Arsenault
156f3fce54
AMDGPU: Handle rewriting VGPR MFMAs with immediate src2 (#153016) 2025-08-21 09:09:24 +09:00
Matt Arsenault
ff5f396dac
AMDGPU: Handle rewriting non-tied MFMA to AGPR form (#153015)
If src2 and dst aren't the same register, to fold a copy
to AGPR into the instruction we also need to reassign src2
to an available AGPR. All the other uses of src2 also need
to be compatible with the AGPR replacement in order to avoid
inserting other copies somewhere else.

Perform this transform, after verifying all other uses are
compatible with AGPR, and have an available AGPR available at
all points (which effectively means rewriting a full chain of
mfmas and load/store at once).
2025-08-21 08:16:56 +09:00
Matt Arsenault
30007a5414
AMDGPU: Fix crash in rewrite AGPR copy MFMA pass on dead valnos (#153915)
Test isn't great, probably won't reliably reproduce the problem
in the future.
2025-08-16 23:09:23 +09:00
Matt Arsenault
9a293530d9
AMDGPU: Handle multiple AGPR MFMA rewrites (#147975)
I have this firing on one of the real examples, need to
produce the tests and check a few edge cases
2025-08-11 23:10:35 +09:00
Matt Arsenault
1f86deb5a4 AMDGPU: Add debug printing for early exit if there are no AGPRs allocated 2025-08-11 09:27:05 +09:00
Matt Arsenault
81f3ddf4a2
AMDGPU: Rewrite VGPR MFMAs to AGPR when directly copied to AGPR class (#152480) 2025-08-08 18:20:21 +09:00
Matt Arsenault
548ca9e976
AMDGPU: Fix asserting on non-register mfma src2 (#150552)
Also validate the subregister, although for the moment this
is redundant since we currently only process full copies.
2025-07-25 10:13:53 +09:00
Matt Arsenault
c8ea114741
AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)
In gfx90a-gfx950, it's possible to emit MFMAs which use AGPRs or VGPRs
for vdst and src2. We do not want to do use the AGPR form, unless
required by register pressure as it requires cross bank register
copies from most other instructions. Currently we select the AGPR
or VGPR version depending on a crude heuristic for whether it's possible
AGPRs will be required. We really need the register allocation to
be complete to make a good decision, which is what this pass is for.
    
This adds the pass, but does not yet remove the selection patterns
for AGPRs. This is a WIP, and NFC-ish. It should be a no-op on any
currently selected code. It also does not yet trigger on the real
examples of interest, which require handling batches of MFMAs at
once.
2025-06-27 21:05:03 +09:00