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9 Commits

Author SHA1 Message Date
Craig Topper
562e021103
[RISCV] Minor refactor of RISCVMoveMerge::mergePairedInsns. (#154467) 
Fold the ARegInFirstPair into the later if/else with the same condition.
Use std::swap so we don't need to repeat operands in the opposite order.
 2025-08-20 09:07:58 -07:00
Craig Topper
d145dc10b6
[RISCV] Reduce code duplication in RISCVMoveMerge::findMatchingInst. NFCI (#154451) 2025-08-19 21:08:57 -07:00
Craig Topper
9465916a61
[RISCV] Stop passing the merge opcode around in RISCVMoveMerger. NFC (#153687) 
What most code wants to know is the direction and we have to decode the
opcode to figure that out. Instead pass the direction around as a bool
and convert to opcode when we create the merge instruction.
 2025-08-14 18:08:23 -07:00
Craig Topper
defbbf0129
[RISCV][MoveMerge] Don't copy kill flag when moving past an instruction that reads the register. (#153644) 
If we're moving the second copy before another instruction that reads
the copied register, we need to clear the kill flag on the combined
move.

Fixes #153598.
 2025-08-14 14:52:54 -07:00
Sam Elliott
e49180d84c
[RISCV] Xqccmp Code Generation (#128815) 
This adds support for Xqccmp to the following passes:
- Prolog Epilog Insertion - reusing much of the existing push/pop logic,
but extending it to cope with frame pointers and reorder the CFI
information correctly.
- Move Merger - extending it to support the `qc.` variants of the
double-move instructions.
- Push/Pop Optimizer - extending it to support the `qc.` variants of the
pop instructions.

The testing is based on existing Zcmp tests, but I have put them in
separate files as some of the Zcmp tests were getting quite long.
 2025-03-05 10:59:45 -08:00
Craig Topper
4162a9bca4 [RISCV] Cleanup pass initialization. 
Remove redundant initializations from pass constructors that were
already being initialized by LLVMInitializeRISCVTarget().
 2023-12-07 18:21:38 -08:00
Craig Topper
44d4f975e4 [RISCV] Replace RISCV -> RISC-V in comments. NFC 
I did this once previously, but more uses have crept in.
 2023-10-21 10:52:24 -07:00
Alex Bradbury
71299921d5 [RISCV][NFC] Adjust RISCVMoveMerge.cpp header to match standard style 
* 80 columns
* Fix name of file (RISCVMoveMerger.cpp vs RISCVMoveMerge.cpp)
* `//===--` prefix rather than center-aligned text.
 2023-06-27 13:35:41 +01:00
WuXinlong
c9e08fa606 [RISCV] Add a pass to merge moving parameter registers instructions for Zcmp 
This patch adds a pass to generate `cm.mvsa01` & `cm.mva01s`.

RISCVMoveOptimizer.cpp which combines two mv inst into one cm.mva01s or cm.mva01s.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D150415
 2023-06-21 15:41:51 +08:00