4492 Commits

Author SHA1 Message Date
Eric Christopher
faf5c76114 80-col.
llvm-svn: 109205
2010-07-23 01:05:59 +00:00
Gabor Greif
59f9970ba5 keep in 80 cols
llvm-svn: 109122
2010-07-22 17:18:03 +00:00
Gabor Greif
dde79d8f1a mass elimination of reliance on automatic iterator dereferencing
llvm-svn: 109103
2010-07-22 13:36:47 +00:00
Evan Cheng
bf32e54bac Re-apply r109079 with fix.
llvm-svn: 109083
2010-07-22 06:24:48 +00:00
Owen Anderson
6c55cccf87 Revert r109079, which broke a lot of CodeGen tests.
llvm-svn: 109082
2010-07-22 06:01:28 +00:00
Evan Cheng
bd81bff672 Initialize RegLimit only when register pressure is being tracked.
llvm-svn: 109079
2010-07-22 05:18:41 +00:00
Evan Cheng
285903853f More register pressure aware scheduling work.
llvm-svn: 109064
2010-07-21 23:53:58 +00:00
Evan Cheng
a77f3d3b37 Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
llvm-svn: 108991
2010-07-21 06:09:07 +00:00
Dan Gohman
b5e918dc05 After a custom inserter, in a block which has constant instructions,
update the current basic block in addition to the current insert
position, so that they remain consistent. This fixes rdar://8204072.

llvm-svn: 108765
2010-07-19 22:48:56 +00:00
Evan Cheng
10f99a3490 ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
llvm-svn: 108761
2010-07-19 22:15:08 +00:00
Evan Cheng
7a135510e3 Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64.
This property will be used by the register pressure tracking instruction scheduler.

llvm-svn: 108735
2010-07-19 18:47:01 +00:00
Owen Anderson
9c271e2835 Remove r108639 now that it is handled by InstCombine instead.
llvm-svn: 108688
2010-07-19 08:10:24 +00:00
Owen Anderson
f7f9c8a2f7 Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions.
I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this.

This fixed <rdar://problem/8197504>.

llvm-svn: 108639
2010-07-18 08:47:54 +00:00
Eric Christopher
0baaa9bcc1 Propagate alloca alignment information via variable size object frame
information.

No functional change yet.

llvm-svn: 108583
2010-07-17 00:28:22 +00:00
Dan Gohman
1e936277c3 Revert r108369, sorting llvm.dbg.declare information by source position,
since it doesn't work for front-ends which don't emit column information
(which includes llvm-gcc in its present configuration), and doesn't
work for clang for K&R style variables where the variables are declared
in a different order from the parameter list.

Instead, make a separate pass through the instructions to collect the
llvm.dbg.declare instructions in order. This ensures that the debug
information for variables is emitted in this order.

llvm-svn: 108538
2010-07-16 17:54:27 +00:00
Dan Gohman
103c4ebea5 Use the source-order scheduler instead of the "fast" scheduler at -O0,
because it's more likely to keep debug line information in its original
order.

llvm-svn: 108496
2010-07-16 02:01:19 +00:00
Dale Johannesen
bfd4fd7bb7 The SelectionDAGBuilder's handling of debug info, on rare
occasions, caused code to be generated in a different order.
All cases I've seen involved float softening in the type
legalizer, and this could be perhaps be fixed there, but
it's better not to generate things differently in the first
place.  7797940 (6/29/2010..7/15/2010).

llvm-svn: 108484
2010-07-16 00:02:08 +00:00
Bill Wendling
4bda1c8e68 Revert. This isn't the correct way to go.
llvm-svn: 108478
2010-07-15 23:42:21 +00:00
Bill Wendling
973dc3b1d8 Handle code gen for the unreachable instruction if it's the only instruction in
the function. We'll just turn it into a "trap" instruction instead.

The problem with not handling this is that it might generate a prologue without
the equivalent epilogue to go with it:

$ cat t.ll
define void @foo() {
entry:
  unreachable
}
$ llc -o - t.ll -relocation-model=pic -disable-fp-elim -unwind-tables
        .section        __TEXT,__text,regular,pure_instructions
        .globl  _foo
        .align  4, 0x90
_foo:                                   ## @foo
Leh_func_begin0:
## BB#0:                                ## %entry
        pushq   %rbp
Ltmp0:
        movq    %rsp, %rbp
Ltmp1:
Leh_func_end0:
...

The unwind tables then have bad data in them causing all sorts of problems.

Fixes <rdar://problem/8096481>.

llvm-svn: 108473
2010-07-15 23:32:40 +00:00
Evan Cheng
55f0c6b9fc Split -enable-finite-only-fp-math to two options:
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.

llvm-svn: 108465
2010-07-15 22:07:12 +00:00
Devang Patel
df09db62e2 Fix crash reported in PR7653.
llvm-svn: 108441
2010-07-15 18:45:27 +00:00
Eric Christopher
474e56a2bf 80-col.
llvm-svn: 108381
2010-07-14 23:41:32 +00:00
Dan Gohman
c12a6731c5 Properly restore DebugLoc after leaving the local constant area.
llvm-svn: 108364
2010-07-14 22:01:31 +00:00
Dan Gohman
042523340b Delete fast-isel's trivial load optimization; it breaks debugging because
it can look past points where a debugger might modify user variables.

llvm-svn: 108336
2010-07-14 17:25:37 +00:00
Dan Gohman
1f471435f8 Don't propagate debug locations to instructions for materializing
constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.

llvm-svn: 108302
2010-07-14 01:07:44 +00:00
Dale Johannesen
caca5488dc In inline asm treat indirect 'X' constraint as 'm'.
This may not be right in all cases, but it's better
than asserting which it was doing before.  PR 7528.

llvm-svn: 108268
2010-07-13 20:17:05 +00:00
Rafael Espindola
a18c5a0e5e Fix a typo and fit in 80 columns. Found by Bob Wilson.
llvm-svn: 108164
2010-07-12 18:11:17 +00:00
Duncan Sands
41b4a6b36a Convert some tab stops into spaces.
llvm-svn: 108130
2010-07-12 08:16:59 +00:00
Jakob Stoklund Olesen
51642aea77 Use COPY for fast-isel bitconvert, but don't create cross-class copies.
This doesn't change the behavior of SelectBitcast for X86.

llvm-svn: 108073
2010-07-11 05:16:54 +00:00
Rafael Espindola
a76eccf815 Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

llvm-svn: 108072
2010-07-11 04:01:49 +00:00
Jakob Stoklund Olesen
7147ab9e78 Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.
This assumes that the registers can be copied which is probably a safe
assumption.

llvm-svn: 108070
2010-07-11 03:31:05 +00:00
Jakob Stoklund Olesen
3bb1267431 Use COPY in FastISel everywhere it is safe and trivial.
The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.

llvm-svn: 108069
2010-07-11 03:31:00 +00:00
Dan Gohman
a64a323564 Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;
if a block is split (by a custom inserter), the insert point may be in a
different block than it was originally. This fixes 32-bit llvm-gcc
bootstrap builds, and I haven't been able to reproduce it otherwise.

llvm-svn: 108060
2010-07-10 22:42:31 +00:00
Jakob Stoklund Olesen
e50d30d586 Emit COPY instructions instead of using copyRegToReg in InstrEmitter,
ScheduleDAGEmit, TwoAddressLowering, and PHIElimination.

This switches the bulk of register copies to using COPY, but many less used
copyRegToReg calls remain.

llvm-svn: 108050
2010-07-10 19:08:25 +00:00
Dan Gohman
fbdba81550 Insert IMPLICIT_DEF instructions at the current insert position, not
at the end of the block.

llvm-svn: 108045
2010-07-10 13:55:45 +00:00
Dan Gohman
d7b5ce3312 Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

llvm-svn: 108039
2010-07-10 09:00:22 +00:00
Bill Wendling
f831d86311 Clarify what mysterious check means.
llvm-svn: 108005
2010-07-09 19:44:12 +00:00
Bob Wilson
6586e9b203 --- Reverse-merging r107947 into '.':
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 107987
2010-07-09 16:37:18 +00:00
Gabor Greif
52617fc462 cache result of operator*
llvm-svn: 107980
2010-07-09 16:08:33 +00:00
Dan Gohman
0b5aa1cdd3 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.

llvm-svn: 107943
2010-07-09 00:39:23 +00:00
Bob Wilson
21eed476e8 Reenable DAG combining for vector shuffles. It looks like it was temporarily
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.

llvm-svn: 107941
2010-07-09 00:38:12 +00:00
Bill Wendling
a992445ff2 Extension of r107506. Make sure that we don't mark a function as having a call
if the inline ASM doesn't need a stack frame.

llvm-svn: 107922
2010-07-08 22:38:02 +00:00
Jakob Stoklund Olesen
00264624a9 Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

llvm-svn: 107879
2010-07-08 16:40:22 +00:00
Benjamin Kramer
0ae3f08c0d Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms.
llvm-svn: 107868
2010-07-08 12:09:56 +00:00
Dan Gohman
e75704369d Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.

llvm-svn: 107850
2010-07-08 01:00:56 +00:00
Dan Gohman
eb9164dc50 Don't forward-declare registers for static allocas, which we'll
prefer to materialize as local constants. This fixes the clang
bootstrap abort.

llvm-svn: 107840
2010-07-07 23:52:58 +00:00
Dan Gohman
1adc499dda Fix -fast-isel-abort to check the right instruction.
llvm-svn: 107839
2010-07-07 23:47:25 +00:00
Evan Cheng
1c349f18f8 Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
llvm-svn: 107820
2010-07-07 22:15:37 +00:00
Dan Gohman
25d5c1b4f8 Not all custom inserters create new basic blocks. If the inserter
didn't create a new block, don't reset the insert position.

llvm-svn: 107813
2010-07-07 21:18:22 +00:00
Dan Gohman
e7ccc51cc1 Implement bottom-up fast-isel. This has the advantage of not requiring
a separate DCE pass over MachineInstrs.

llvm-svn: 107804
2010-07-07 19:20:32 +00:00