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2786 Commits

Author SHA1 Message Date
Chris Lattner
749ca32da1 eliminate the TargetInstrInfo::GetInstSizeInBytes hook. 
ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.

llvm-svn: 109171
 2010-07-22 21:27:00 +00:00
Chris Lattner
dab6888bb1 switch a private implementation of GetFunctionSizeInBytes. 
This is probably not the best way to implement "Force LR to 
be spilled if the Thumb function size is > 2048." do this, 
it should use the branch shortening infrastructure, but I'm
just preserving functionality here.

llvm-svn: 109165
 2010-07-22 21:14:33 +00:00
Xerxes Ranby
ff66cd43c4 ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608 
llvm-svn: 109125
 2010-07-22 17:28:34 +00:00
Chandler Carruth
a1d7516cb7 Mark an assert-only variable as used. 
llvm-svn: 109091
 2010-07-22 08:02:25 +00:00
Chandler Carruth
2f8db38bb3 Fix the generated file name for CMake. 
llvm-svn: 109090
 2010-07-22 08:00:52 +00:00
Chandler Carruth
3180f9f55f Attempt to fix linking issues with CMake. Please review other CMake users, 
especially on other platforms. Is there a better way to fix this.

llvm-svn: 109084
 2010-07-22 06:27:45 +00:00
Owen Anderson
14646cc074 Update CMake files. 
llvm-svn: 109081
 2010-07-22 06:00:01 +00:00
Evan Cheng
3fabe07d4c Fix constant island pass's handling of tBR_JTr. The offset of the instruction does not have to be 4-byte aligned. Rather, it's the offset + 2 that must be aligned since the instruction expands into: 
mov     pc, r1
        .align  2
LJTI0_0_0:
        .long    LBB0_14

This fixes rdar://8213383. No test case since it's not possible to come up with a suitable small one.

llvm-svn: 109076
 2010-07-22 02:09:47 +00:00
Evan Cheng
285903853f More register pressure aware scheduling work. 
llvm-svn: 109064
 2010-07-21 23:53:58 +00:00
Jim Grosbach
965a73a28c For ARM/Darwin, add a dwarf entry indicating whether a function is arm or thumb 
rdar://8202967

llvm-svn: 109057
 2010-07-21 23:03:52 +00:00
Eric Christopher
84bdfd80df Baby steps towards ARM fast-isel. 
llvm-svn: 109047
 2010-07-21 22:26:11 +00:00
Rafael Espindola
4277e14dc4 Fix calling convention on ARM if vfp2+ is enabled. 
llvm-svn: 109009
 2010-07-21 11:38:30 +00:00
Evan Cheng
a77f3d3b37 Teach bottom up pre-ra scheduler to track register pressure. Work in progress. 
llvm-svn: 108991
 2010-07-21 06:09:07 +00:00
Chris Lattner
cbe9856fce prune #includes a little. 
llvm-svn: 108929
 2010-07-20 21:17:29 +00:00
Jim Grosbach
3680f70c9d Using BIC for immediates needs an extra bump for its complexity to get 
instruction selection to prefer it when possible. rdar://7903972

llvm-svn: 108844
 2010-07-20 16:07:04 +00:00
Jim Grosbach
9c7708cc1b Removed un-used code. 
llvm-svn: 108841
 2010-07-20 14:51:32 +00:00
Eric Christopher
4adaccf0bf Constify some arguments. 
llvm-svn: 108812
 2010-07-20 06:52:21 +00:00
Daniel Dunbar
0aff8033c6 Update CMake files. 
llvm-svn: 108787
 2010-07-20 00:08:13 +00:00
Chris Lattner
b792b463af sink the arm implementations of ASmPrinter and MCInstLower 
out of the AsmPrinter directory into libarm.  Now the
ARM InstPrinters depend jsut on the MC stuff, not on vmcore
or codegen.

llvm-svn: 108783
 2010-07-19 23:44:46 +00:00
Evan Cheng
10f99a3490 ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers. 
llvm-svn: 108761
 2010-07-19 22:15:08 +00:00
Jim Grosbach
8d3ba7349c Since ARM emits inline jump tables as part of the ConstantIsland pass, 
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR6581.

llvm-svn: 108730
 2010-07-19 17:20:38 +00:00
Jim Grosbach
d9ad52adff revert so I can get the right PR# in the log message. 
llvm-svn: 108727
 2010-07-19 17:19:40 +00:00
Jim Grosbach
c685756cfb Since ARM emits inline jump tables as part of the ConstantIsland pass, 
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR7499.

llvm-svn: 108722
 2010-07-19 17:18:28 +00:00
Daniel Dunbar
419197cc4d Target: Give the TargetAsmParser access to the TargetMachine. 
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.

llvm-svn: 108664
 2010-07-19 00:33:49 +00:00
Jim Grosbach
b97e2bbe32 Add combiner patterns to more effectively utilize the BFI (bitfield insert) 
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.

llvm-svn: 108608
 2010-07-17 03:30:54 +00:00
Jim Grosbach
6e3b5fa91c add BFI to getTargetNodeName() 
llvm-svn: 108603
 2010-07-17 01:50:57 +00:00
Jim Grosbach
adc81f8ee8 Fix logic think-o 
llvm-svn: 108601
 2010-07-17 01:22:19 +00:00
Eric Christopher
83f250f005 Remove unnecessary check that was subsumed into canRealignStack. 
llvm-svn: 108588
 2010-07-17 00:33:04 +00:00
Eric Christopher
24e3aa011a Make more explicit and add some currently disabled error messages for 
stack realignment on ARM.

Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.

llvm-svn: 108582
 2010-07-17 00:27:24 +00:00
Jim Grosbach
11013eda5a Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction 
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570
 2010-07-16 23:05:05 +00:00
Jakob Stoklund Olesen
8289f78569 Remove the isMoveInstr() hook. 
llvm-svn: 108567
 2010-07-16 22:35:46 +00:00
Jakob Stoklund Olesen
54bcf5049e Use a small local function for a single remaining late isMoveInstr call in 
Thumb2ITBlockPass.

llvm-svn: 108564
 2010-07-16 22:35:32 +00:00
Bill Wendling
499f797cdd Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and 
thus is a much more meaningful name.

llvm-svn: 108563
 2010-07-16 22:20:36 +00:00
Evan Cheng
55f0c6b9fc Split -enable-finite-only-fp-math to two options: 
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.

llvm-svn: 108465
 2010-07-15 22:07:12 +00:00
Eli Friedman
e4be4308a9 Random note about bswap. 
llvm-svn: 108396
 2010-07-15 02:20:38 +00:00
Bob Wilson
0b9aafddc5 Remove restriction on NEON alignment values. Some of the NEON ld/st 
instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.

llvm-svn: 108386
 2010-07-14 23:54:43 +00:00
Benjamin Kramer
92d8998348 Don't pass StringRef by reference. 
llvm-svn: 108366
 2010-07-14 22:38:02 +00:00
Jim Grosbach
a90af1ba38 Improve 64-subtraction of immediates when parts of the immediate can fit 
in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339
 2010-07-14 17:45:16 +00:00
Bob Wilson
1aef53403f Add missing address register update to t2LDM_RET instruction. 
Patch by Brian Lucas. PR7636.

llvm-svn: 108332
 2010-07-14 16:02:13 +00:00
Eli Friedman
c4d70125ee A couple potential optimizations inspired by comment 4 in PR6773. 
llvm-svn: 108328
 2010-07-14 06:58:26 +00:00
Bob Wilson
bad47f62f6 Add support for NEON VMVN immediate instructions. 
llvm-svn: 108324
 2010-07-14 06:31:50 +00:00
Bob Wilson
bd54a53628 The bits in the cmode field of 32-bit VMOV immediate instructions all depend 
of the value of the immediate.

llvm-svn: 108323
 2010-07-14 06:30:44 +00:00
Bob Wilson
103a0dcfe1 Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes. 
Radar 7373643.

llvm-svn: 108303
 2010-07-14 01:22:12 +00:00
Bob Wilson
a3f1901531 Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent 
NEON VMOV-immediate instructions.  This simplifies some things.

llvm-svn: 108275
 2010-07-13 21:16:48 +00:00
Evan Cheng
0cc4ad983d Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. 
llvm-svn: 108258
 2010-07-13 19:27:42 +00:00
Evan Cheng
58066e337d Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles). 
llvm-svn: 108256
 2010-07-13 19:21:50 +00:00
Bob Wilson
c1c6f4796e Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to 
avoid replicated code.

llvm-svn: 108227
 2010-07-13 04:44:34 +00:00
Bob Wilson
8a2bdc8231 Remove some code that doesn't appear to do anything. All the ARM call 
instructions already have implicit defs of LR.  The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.

llvm-svn: 108186
 2010-07-12 20:22:45 +00:00
Duncan Sands
41b4a6b36a Convert some tab stops into spaces. 
llvm-svn: 108130
 2010-07-12 08:16:59 +00:00
Jakob Stoklund Olesen
0961c55161 RISC architectures get their memory operand folding for free. 
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

llvm-svn: 108099
 2010-07-11 19:19:13 +00:00