11597 Commits

Author SHA1 Message Date
Aaron Ballman
7548cec16f
[www][docs] Remove last mentions of IRC (#139076)
It's the end of an era. The IRC channel was previously where the
community gathered to discuss technical topics but is now a ghost town
where the primary activity is moderators (me) kickbanning the same
individual dozens of times a day for CoC violations and the secondary
activity is telling the occasional person to come to Discord for help.
The number of people engaging on IRC for the community's intended
purposes seems to be roughly one person a month.

So this removes all remaining mentions of IRC from our documentation so
that it no longer appears to be an "official" channel for communicating
with the community. It also removes IRC handles from the various
maintainers lists, since those would stand out as confusing
anachronisms.

The IRC channel topic already recommends people come to the Discord
server. There is no way to "shut down" an IRC channel such that it no
longer exists, so the channel will continue to exist on OFTC, but will
be unmoderated.

(This was previously discussed in https://discourse.llvm.org/c/llvm/5
but some mentions persisted.)
2025-05-08 09:40:33 -04:00
Cullen Rhodes
da8d60fbfe
[docs][nfc] Fix code-formatting in UB docs (#139079) 2025-05-08 14:27:46 +01:00
Matt Arsenault
4d60c6d9b2
Reapply "IR: Remove reference counts from ConstantData (#137314)" (#138962)
This reverts commit 0274232b87177779e5c985eca06df22bf140f6cb.
2025-05-08 08:02:54 +02:00
Matt Arsenault
9383fb23e1
Reapply "IR: Remove uselist for constantdata (#137313)" (#138961)
Reapply "IR: Remove uselist for constantdata (#137313)"

This reverts commit 5936c02c8b9c6d1476f7830517781ce8b6e26e75.

Fix checking uselists of constants in assume bundle queries
2025-05-08 08:00:09 +02:00
Craig Topper
e0e3d05a2e
[RISCV] Fix the link to the XAndesPerf specification. NFC (#138804)
We need to use 2 underscores after the URL like the other specification
links.
2025-05-07 17:38:11 -07:00
Kirill Stoimenov
5936c02c8b Revert "IR: Remove uselist for constantdata (#137313)"
Possibly breaks the build: https://lab.llvm.org/buildbot/#/builders/24/builds/8119

This reverts commit 87f312aad6ede636cd2de5d18f3058bf2caf5651.
2025-05-07 00:07:55 +00:00
Kirill Stoimenov
0274232b87 Revert "IR: Remove reference counts from ConstantData (#137314)"
This reverts commit 51a3bd919d68a8fb1b026377d6e86b1523d37433.

Possible breaks the build: https://lab.llvm.org/buildbot/#/builders/24/builds/8119/steps/9/logs/stdio
2025-05-07 00:07:55 +00:00
Matt Arsenault
51a3bd919d
IR: Remove reference counts from ConstantData (#137314)
This is a follow up change to eliminating uselists for ConstantData.
In the previous revision, ConstantData had a replacement reference count
instead of a uselist. This reference count was misleading, and not useful
in the same way as it would be for another value. The references may not
have even been in the current module, since these are shared throughout
the LLVMContext.

This doesn't space leak any more than we previously did; nothing was
attempting to garbage collect unused constants.

Previously the use_empty, and hasNUses type of APIs were supported through
the reference count. These now behave as if the uses are always empty.
Ideally it would be illegal to inspect these, but this forces API complexity
into quite a few places. It may be doable to make it illegal to check these
counts, but I would like there to be a targeted fuzzing effort to make sure
every transform properly deals with a constant in every operand position.

All tests pass if I turn the hasNUses* and getNumUses queries into assertions,
only hasOneUse in particular appears to hit in some set of contexts. I've
added unit tests to ensure logical consistency between these cases
2025-05-06 17:23:59 +02:00
Matt Arsenault
87f312aad6
IR: Remove uselist for constantdata (#137313)
This is a resurrected version of the patch attached to this RFC:

https://discourse.llvm.org/t/rfc-constantdata-should-not-have-use-lists/42606

In this adaptation, there are a few differences. In the original patch, the Use's
use list was replaced with an unsigned* to the reference count in the value. This
version leaves them as null and leaves the ref counting only in Value.

Remove use-lists from instances of ConstantData (which are shared
across modules and have no operands).

To continue supporting most of the use-list API, store a ref-count in
place of the use-list; this is for API like Value::use_empty and
Value::hasNUses.  Operations that actually need the use-list -- like
Value::use_begin -- will assert.

This change has three benefits:

 1. The compiler output cannot in any way depend on the use-list order
    of instances of ConstantData.

 2. There's no use-list traffic when adding and removing simple
    constants from operand lists (although there is ref-count traffic;
    YMMV).

 3. It's cheaper to serialize use-lists (since we're no longer
    serializing the use-list order of things like i32 0).

The downside is that you can't look at all the users of ConstantData,
but traversals of users of i32 0 are already ill-advised.

Possible follow-ups:
  - Track if an instance of a ConstantVector/ConstantArray/etc. is known
    to have all ConstantData arguments, and drop the use-lists to
    ref-counts in those cases.  Callers need to check Value::hasUseList
    before iterating through the use-list.
  - Remove even the ref-counts.  I'm not sure they have any benefit
    besides minimizing the scope of this commit, and maintaining the
    counts is not free.

Fixes #58629

Co-authored-by: Duncan P. N. Exon Smith <dexonsmith@apple.com>
2025-05-06 17:20:37 +02:00
Paschalis Mpeis
a8344a95c7
[llvm][docs] Reorder Stacked PR approaches in GitHub.rst (#138126)
The 'user branches' approach now appears before the 'dependency note'
approach, as it makes reviewing easier.

Add notes on requiring commit access for the former approach.
2025-05-06 12:29:04 +01:00
Kristof Beyls
f2f4eac6c5
Clarify ban evasion policy (#137298)
This documents what the Code of Conduct committee has decided to do when
an attempt to evade a ban is detected.
2025-05-06 09:40:03 +01:00
Nikita Popov
562a4559ee
[ProgrammersManual] Update report_fatal_error docs (#138502)
Update docs for https://github.com/llvm/llvm-project/pull/138251.
Mention reportFatalInternalError and reportFatalUsageError in the
respective sections of the documentation.
2025-05-06 09:58:10 +02:00
Min-Yih Hsu
ca1ebff9de
[RISCV] Add processor definition for SiFive P870 (#137725)
SiFive P870 is a RVA23 compatible high-performance CPU:
https://www.sifive.com/cores/performance-p800

Scheduling model will be added in a follow-up PR.
2025-05-05 18:48:21 -07:00
Matt Arsenault
aa10f879dc
llvm-reduce: Fix trailing whitespace in command guide (#138240) 2025-05-02 10:35:53 +02:00
Nikita Popov
a8ec6e8788
[IR] Require that global value initializers are sized (#137358)
While external globals can be unsized, I don't think an unsized
initializer makes sense.

It seems like the backend currently ends up treating this as a zero-size
global. If people want that behavior, they should declare it as such.
2025-05-02 09:52:39 +02:00
David Spickett
09488bcfba
[lldb] Disable statusline on Windows (#138111)
Something to do with control code handling in Windows terminals breaks
the statusline in various ways. It makes LLDB unusable and even if you
set the setting to disable statusline, it's too late, and the terminal
session is now in a weird state.

See https://github.com/llvm/llvm-project/issues/134846 for more details.

Until we figure this out, don't allow it to be used on Windows.
2025-05-01 16:40:47 +01:00
Jonathan Thackray
6e49f73825
Reland [llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (#137701)
This patch adds support for LLVM IR atomicrmw `fmaximum` and `fminimum`
instructions.

These mirror the `llvm.maximum.*` and `llvm.minimum.*` instructions, but
are atomic and use IEEE754 2019 handling for NaNs, which is different to
`fmax` and `fmin`. See:
     https://llvm.org/docs/LangRef.html#llvm-minimum-intrinsic
for more details.

Future changes will allow this LLVM IR to be lowered to specialised
assembler instructions on suitable targets, such as AArch64.
2025-04-30 22:06:37 +01:00
Kip Hamiltons
e87aaaf327
[LangRef] Minor editorial fixes (#137782) 2025-04-30 15:10:48 +02:00
Nikita Popov
6feb4a8ef4
[IR] Don't allow values of opaque type (#137625)
Consider opaque types as non-first-class types, i.e. do not allow SSA
values to have opaque type.
2025-04-30 15:01:00 +02:00
Stephen Tozer
92195f6fc8 Reapply "[DLCov] Implement DebugLoc coverage tracking (#107279)"
Reapplied after fixing the config issue that was causing issues following
the previous merge.

This reverts commit fdbf073a86573c9ac4d595fac8e06d252ce1469f.
2025-04-30 11:39:29 +01:00
Nikita Popov
38cb7d5e75
[IR] Don't allow label arguments (#137799)
We currently accept label arguments to inline asm calls. This support
predates both blockaddresses and callbr and is only covered by one X86
test. Remove it in favor of callbr (or at least blockaddress, though
that cannot guarantee correct codegen, just like using block labels
directly can't).

I didn't bother implementing bitcode upgrade support for this, but I can
add it if desired.
2025-04-30 09:11:36 +02:00
Jonathan Thackray
7ee0097b48
Revert "[llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions" (#137657)
Reverts llvm/llvm-project#136759 due to bad interaction with c792b25e4
2025-04-28 16:53:36 +01:00
Jonathan Thackray
ba420d8122
[llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (#136759)
This patch adds support for LLVM IR atomicrmw `fmaximum` and `fminimum`
instructions.

These mirror the `llvm.maximum.*` and `llvm.minimum.*` instructions, but
are atomic and use IEEE754 2019 handling for NaNs, which is different to
`fmax` and `fmin`. See:
     https://llvm.org/docs/LangRef.html#llvm-minimum-intrinsic
for more details.

Future changes will allow this LLVM IR to be lowered to specialised
assembler instructions on suitable targets, such as AArch64.
2025-04-28 15:31:44 +01:00
Jim Lin
6ba1a62a6c
[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler.

Relocation and fixup for the branch and gp-implied instructions will be
added in a later patch.
2025-04-28 17:23:51 +08:00
i-ky
6f6af49938
Clarify lit's definition of failure and conditions when it exits with exit code 1 (#136190)
Documentation of when `lit` exits with code 1 is out of date.

It is no longer just "FAIL or XPASS", there are more failure types:

b30100b87f/llvm/utils/lit/lit/Test.py (L51-L55)

Exit code can also be affected by `--ignore-fail` option:

b30100b87f/llvm/utils/lit/lit/main.py (L154-L162)

This PR extracts a clear definition of "failure" from the description of
`--report-failures-only` option:

b30100b87f/llvm/docs/CommandGuide/lit.rst (L194-L196)
...puts it into "Test Status Results" section and references it when
describing exit codes and `--ignore-fail` option.
2025-04-28 07:06:42 +01:00
Quinton Miller
165acd3734
[LLVM-C] Support debug info for enumerators of arbitrary sizes (#76735)
Since `LLVMDIBuilderCreateEnumerator` only supports up to 64 bits, this
PR adds a new `LLVMDIBuilderCreateEnumeratorOfArbitraryPrecision`
function that takes an arbitrary number of words, based on
`LLVMConstIntOfArbitraryPrecision`. This allows even larger enumeration
types to represent their values exactly. (It seems LLVM should already
support i128 enums since 13.0.0.)
2025-04-26 21:47:09 +02:00
Sam Elliott
cfc5baf6e6
[RISCV] SiFive CLIC Support (#132481)
This Change adds support for two SiFive vendor attributes in clang:
- "SiFive-CLIC-preemptible"
- "SiFive-CLIC-stack-swap"

These can be given together, and can be combined with "machine", but
cannot be combined with any other interrupt attribute values.

These are handled primarily in RISCVFrameLowering:
- "SiFive-CLIC-stack-swap" entails swapping `sp` with `sf.mscratchcsw`
  at function entry and exit, which holds the trap stack pointer.
- "SiFive-CLIC-preemptible" entails saving `mcause` and `mepc` before
  re-enabling interrupts using `mstatus`. To save these, `s0` and `s1`
  are first spilled to the stack, and then the values are read into
  these registers. If these registers are used in the function, their
  values will be spilled a second time onto the stack with the generic
  callee-saved-register handling. At the end of the function interrupts
  are disabled again before `mepc` and `mcause` are restored.

This Change also adds support for the following two experimental
extensions, which only contain CSRs:
- XSfsclic - for SiFive's CLIC Supervisor-Mode CSRs
- XSfmclic - for SiFive's CLIC Machine-Mode CSRs

The latter is needed for interrupt support.

The CFI information for this implementation is not correct, but I'd
prefer to correct this in a follow-up. While it's unlikely anyone wants
to unwind through a handler, the CFI information is also used by
debuggers so it would be good to get it right.

Co-authored-by: Ana Pazos <apazos@quicinc.com>
2025-04-25 17:12:27 -07:00
cor3ntin
320ec7fa7f
[Documentation] Always use SVG for dot-generated doxygen images. (#136843)
Despite our attempt (build-docs.sh)
to build the documentation with SVG,
it still uses PNG https://llvm.org/doxygen/classllvm_1_1StringRef.html,

and that renders terribly on any high dpi display.

SVG leads to smasller installation and works fine
on all browser (that has been true for _a while_
https://caniuse.com/svg), so this patch just unconditionally build all
dot graphs as SVG in all subprojects and remove the option.
2025-04-25 14:13:17 +02:00
Pierre van Houtryve
c792b25e47
[GlobalISel] Add combine action for C++ combine rules (#135941)
Adds a `combine` action (DAG operator) which allows for easy definition of
combine rule that only match one or more instructions, and defer all remaining
match/apply logic to C++ code.

This avoids the need for split match/apply function in such cases. One function
can do the trick as long as it returns `true` if it changed any code.

This is implemented as syntactic sugar over match/apply. The combine rule is
just a match pattern BUT every C++ pattern inside is treated as an "apply" function.
This makes it fit seamlessly with the current backend.

Fixes #92410
2025-04-25 12:10:02 +02:00
Quinton Miller
86cca005a1
[llvm-c] Add LLVMConstDataArray and LLVMGetRawDataValues (#129440)
Resolves #129439.

The addition to `echo.ll` is for testing `ConstantArray`, because every
other array in that file is in fact a `ConstantDataArray` and now takes
the new code path in `echo.cpp`.
2025-04-25 10:01:52 +02:00
T-Tie
9c2190eb5d
[RISCV] Add support for Ziccamoc (#136694)
Support for Ziccamoc is added in this pr.
Specification link:
https://drive.google.com/file/d/12QKRm92cLcEk8-5J9NI91m0fAQOxqNAq/view

---------

Co-authored-by: Tie <Tie@llvm.com>
2025-04-25 13:49:48 +08:00
Yingwei Zheng
38ad9266b6
[LangRef] Clarify the behavior of select with FP poison-generating flags (#137131)
RFC link:
https://discourse.llvm.org/t/rfc-clarify-the-behavior-of-select-with-fp-poison-generating-flags/85974

Actually, it does not conflict with the definition of FMF if we
interpret a select as `applyFMF(select cond, applyFMF(TrueArm),
applyFMF(FalseArm))`.
2025-04-25 13:47:08 +08:00
Stephen Tozer
fdbf073a86 Revert "[DLCov] Implement DebugLoc coverage tracking (#107279)"
This reverts commit a9d93ecf1f8d2cfe3f77851e0df179b386cff353.

Reverted due to the commit including a config in LLVM headers that is not
available outside of the llvm source tree.
2025-04-25 00:36:28 +01:00
Stephen Tozer
a9d93ecf1f
[DLCov] Implement DebugLoc coverage tracking (#107279)
This is part of a series of patches that tries to improve DILocation bug
detection in Debugify; see the review for more details. This is the patch
that adds the main feature, adding a set of `DebugLoc::get<Kind>`
functions that can be used for instructions with intentionally empty
DebugLocs to prevent Debugify from treating them as bugs, removing the
currently-pervasive false positives and allowing us to use Debugify (in
its original DI preservation mode) to reliably detect existing bugs and
regressions. This patch does not add uses of these functions, except for
once in Clang before optimizations, and in
`Instruction::dropLocation()`, since that is an obvious case that
immediately removes a set of false positives.
2025-04-24 19:41:25 +01:00
Jay Foad
2bc6f9d4b6
[TableGen] Only store direct superclasses in Record (#123072)
In Record only store the direct superclasses instead of all
superclasses. getSuperClasses recurses to find all superclasses when
necessary.

This gives a small reduction in memory usage. On lib/Target/X86/X86.td I
measured about 2.0% reduction in total bytes allocated (measured by
valgrind) and 1.3% reduction in peak memory usage (measured by
/usr/bin/time -v).

---------

Co-authored-by: Min-Yih Hsu <min@myhsu.dev>
2025-04-24 18:57:51 +01:00
Jim Lin
5981be7692
[RISCV] Add Andes A45/AX45 processor definition (#136832)
Andes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline
linux-capable CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA
extensions. They are developed by Andes Technology
https://www.andestech.com, a RISC-V IP provider.

The overviews for A45/AX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45/

Scheduling model will be implemented in a later PR.
2025-04-24 09:16:12 +08:00
Robert O'Callahan
239718055d
[lldb] Implement CLI support for reverse-continue (#132783)
This introduces the options "-F/--forward" and "-R/--reverse" to
`process continue`.

These only work if you're running with a gdbserver backend that supports
reverse execution, such as rr. For testing we rely on the fake
reverse-execution functionality in `lldbreverse.py`.
2025-04-23 16:16:30 -07:00
Vyacheslav Levytskyy
8c47f23232
[SPIRV] Support for the SPV_INTEL_subgroup_matrix_multiply_accumulate SPIR-V extension (#135225)
Adds support for the SPV_INTEL_subgroup_matrix_multiply_accumulate
SPIR-V extension according to
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_subgroup_matrix_multiply_accumulate.asciidoc
2025-04-23 12:11:01 +02:00
Jim Lin
832ca744f2
[RISCV] Add Andes N45/NX45 processor definition (#136670)
Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU
architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA
extensions. They are developed by Andes Technology
https://www.andestech.com, a RISC-V IP provider.

The overviews for N45/NX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/

Scheduling model will be implemented in a later PR.
2025-04-23 14:16:23 +08:00
modiking
3d04da5bc0
[NVPTX] Add support for Shared Cluster Memory address space [2/2] (#136768)
Adds support for new Shared Cluster Memory Address Space
(SHARED_CLUSTER, addrspace 7). See
https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#distributed-shared-memory
for details.

Follow-up to https://github.com/llvm/llvm-project/pull/135444

1. Update existing codegen/intrinsics in LLVM and MLIR that now use this
address space
2. Auto-upgrade previous intrinsics that used SMEM (addrspace 3) but
were really taking in a shared cluster pointer to the new address space
2025-04-22 16:50:45 -07:00
Andrew Rogers
c04958381e
[llvm] add LLVM_ABI_FRIEND macro for friend function decls (#136595)
## Purpose
Introduce a new `LLVM_ABI_FRIEND` macro to `llvm/Support/Compiler.h` for
annotating `friend` function declarations for DLL export.

## Overview
1. Add a new `LLVM_ABI_FRIEND` macro, which behaves identically to the
existing `LLVM_ABI` macro on Windows and compiles to nothing on other
platforms.
2. Update existing documentation to describe proper usage of the
`LLVM_ABI_FRIEND` annotation.

## Background
* MSVC issues a warning when it encounters a `friend` function
declaration that does not match the DLL import/export annotation of the
original function.
* When compiling ELF and Mach-O shared libraries, `friend` function
declarations with visibility annotations produce compilation errors
(GCC) and warnings (Clang).
* Additional context on the effort to annotate LLVM's public interface
is in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307).
2025-04-22 09:49:18 -07:00
Cyndy Ishida
a5a6ae12a4
[docs][CoC] Update verbiage about appeal process (#136715)
Often, when the CoC investigates incidents, most members are available
to discuss & come to a unanimous decision. In the event of an appeal, we
agreed that the effective way to investigate would be for the committee
to consider evidence that was missed in the initial decision-making.
Update the Response guide to reflect this.
2025-04-22 09:04:02 -07:00
Iris
c6071805d4
[docs] Fix typo in GitHub.rst 2025-04-22 23:50:56 +08:00
Fabian Ritter
784dc16088
[LangRef][IR] Fix default AS documentation for allocas without explicit AS (#135942)
So far, the Language Reference said that the alloca address space from
the datalayout is used if no explicit address space is provided, which
is not what the LLParser and the AsmWriter implement. This patch adjusts
the documentation to match the implementation: The default AS 0 is used
if none is explicitly specified.

This is an alternative to PR #135786, which would change the parser's
behavior to match the Language Reference instead.
2025-04-22 08:32:03 +02:00
Liao Chunyu
9e26c797ae
[RISCV] Add smcntrpmf extension (#136556)
spec: https://github.com/riscvarchive/riscv-smcntrpmf
2025-04-22 12:34:39 +08:00
Jonas Devlieghere
f86953c733
[docs] Correct my email address 2025-04-20 19:35:56 -07:00
Chyaka
0e3e0bf42c
[RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (#123193)
XiangShan-KunMingHu is the third generation of Open-source
high-performance RISC-V processor developed by Beijing Institute of Open
Source Chip (BOSC) , and its latest version is V2R2.

The KunMingHu manual is now available at
https://github.com/OpenXiangShan/XiangShan-User-Guide/releases.
It will be updated on the official XiangShan documentation site:
https://docs.xiangshan.cc/zh-cn/latest

You can find the corresponding ISA extension from the XiangShan Github
repository:
https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala

If you want to track the latest performance data of KunMingHu, please
check XiangShan Biweekly: https://docs.xiangshan.cc/zh-cn/latest/blog

This PR adds the processor definition for KunMingHu V2R2, developed by
the XSCC team https://github.com/orgs/OpenXiangShan/teams/xscc.

The scheduling model for XiangShan-KunMingHu V2R2 will be submitted in a
subsequent PR.

---------

Co-authored-by: Shenglin Tang <tangshenglin@ict.ac.cn>
Co-authored-by: Xu, Zefan <ceba_robot@outlook.com>
Co-authored-by: Tang Haojin <tanghaojin@outlook.com>
2025-04-21 10:06:43 +08:00
Eli Friedman
711301066c
[LangRef] Add a description of the semantics of call signatures. (#136189)
This doesn't introduce anything new; it's just a reflection of the
semantics we've already had for many years.

Per discussion on #63484.
2025-04-18 09:24:54 -07:00
amordo
35e6ca47c1
[docs] Add TOC for InstCombine contributor guide (#136293) 2025-04-18 15:35:02 +02:00
vporpo
767c8c1bad
[docs][SandboxIR] Fix cross-reference to sandbox vectorizer (#133768)
The cross-reference used to point to a label in the auto-vectorization
document.
2025-04-17 15:46:42 -07:00