5118 Commits

Author SHA1 Message Date
David Green
06d2d1e156
[ARM] Protect against odd sized vectors in isVTRNMask and friends (#153413)
Fixes the issue reported on #153138, where odd-sized vectors would cause
the checks to iterate off the end of the mask.
2025-08-13 20:57:46 +01:00
Philip Reames
4d629f9744
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
In review of bbde6b, I had originally proposed that we support the
legacy text format. As review evolved, it bacame clear this had been a
bad idea (too much complexity), but in order to let that patch finally
move forward, I approved the change with the variant. This change undoes
the variant, and updates all the tests to just use the array form.
2025-08-12 11:23:05 -07:00
Elizaveta Noskova
bbde6be841
[llvm] Support multiple save/restore points in mir (#119357)
Currently mir supports only one save and one restore point
specification:

```
  savePoint:       '%bb.1'
  restorePoint:    '%bb.2'
```

This patch provide possibility to have multiple save and multiple
restore points in mir:

```
  savePoints:
    - point:           '%bb.1'
  restorePoints:
    - point:           '%bb.2'
```

Shrink-Wrap points split Part 3.
RFC:
https://discourse.llvm.org/t/shrink-wrap-save-restore-points-splitting/83581

Part 1: https://github.com/llvm/llvm-project/pull/117862
Part 2: https://github.com/llvm/llvm-project/pull/119355
Part 4: https://github.com/llvm/llvm-project/pull/119358
Part 5: https://github.com/llvm/llvm-project/pull/119359
2025-08-12 16:34:29 +03:00
Trevor Gross
00c4be3c9e
[Test] Add and update tests for lrint/llrint (NFC) (#152662)
Many backends are missing either all tests for lrint, or specifically
those for f16, which currently crashes for `softPromoteHalf` targets.
For a number of popular backends, do the following:

* Ensure f16, f32, f64, and f128 are all covered
* Ensure both a 32- and 64-bit target are tested, if relevant
* Add `nounwind` to clean up CFI output
* Add a test covering the above if one did not exist
* Always specify the integer type in intrinsic calls

There are quite a few FIXMEs here, especially for `f16`, but much of
this will be resolved in the near future.
2025-08-12 09:56:51 +09:00
AZero13
6a425f1e54
[ARM] Have custom lowering for ucmp and scmp (#149315)
Limited to non-thumb1 for scmp at the moment, since there is no good way
to do it.
2025-08-08 06:51:18 +01:00
eleviant
907b7d0f07
[ARM] Fix inline asm register validation for vector types (#152175)
Patch allows following piece of code to be successfully compiled:
```
register uint8x8_t V asm("d3") = vdup_n_u8(0xff);
```
2025-08-06 10:30:49 +02:00
Matt Arsenault
1392edcc07
ARM: Remove idiv runtime call aliases (#152098)
Really only the i32 variants exist. We don't need synthetic
aliases for illegal types which will be promoted.
2025-08-05 17:49:22 +09:00
AZero13
23022a4683
[SelectionDAG] Move sign pattern check from AArch64 and ARM to general SelectionDAG (#151736)
This works on all cases much like the XOR case above it in SelectionDAG.
2025-08-01 14:46:51 -07:00
Simon Pilgrim
6a8a279882 [ARM] nop_concat_vectors.ll - regenerate test checks 2025-08-01 12:27:11 +01:00
Prabhu Rajasekaran
17ccb849f3
[llvm] Extract and propagate callee_type metadata
Update MachineFunction::CallSiteInfo to extract numeric CalleeTypeIds
from callee_type metadata attached to indirect call instructions.

Reviewers: nikic, ilovepi

Reviewed By: ilovepi

Pull Request: https://github.com/llvm/llvm-project/pull/87575
2025-07-30 14:56:39 -07:00
Fabian Ritter
ef6eaa045a
[GISel] Introduce MIFlags::InBounds (#150900)
This flag applies to G_PTR_ADD instructions and indicates that the operation
implements an inbounds getelementptr operation, i.e., the pointer operand is in
bounds wrt. the allocated object it is based on, and the arithmetic does not
change that.

It is set when the IRTranslator lowers inbounds GEPs (currently only in some
cases, to be extended with a future PR), and in the
(build|materialize)ObjectPtrOffset functions.

Inbounds information is useful in ISel when we have instructions that perform
address computations whose intermediate steps must be in the same memory region
as the final result. A follow-up patch will start using it for AMDGPU's flat
memory instructions, where the immediate offset must not affect the memory
aperture of the address.

This is analogous to a concurrent effort in SDAG: #131862
(related: #140017, #141725).

For SWDEV-516125.
2025-07-30 13:01:23 +02:00
woruyu
d3b2bda19c
[utils][UpdateTestChecks] update_llc_test_checks.py - armv7-apple-darwin triple no longer working (#150906)
### Summary
This PR resolves https://github.com/llvm/llvm-project/issues/150207
2025-07-30 08:01:33 +01:00
Fabian Ritter
d64240b5c6
[GISel] Introduce MachineIRBuilder::(build|materialize)ObjectPtrOffset (#150392)
These functions are for building G_PTR_ADDs when we know that the base
pointer and the result are both valid pointers into (or just after) the
same object. They are similar to SelectionDAG::getObjectPtrOffset.

This PR also changes call sites of the generic (build|materialize)PtrAdd
functions that implement pointer arithmetic to split large memory
accesses to the new functions. Since memory accesses have to fit into an
object in memory, pointer arithmetic to an offset into a large memory
access also yields an address in that object.

Currently, these (build|materialize)ObjectPtrOffset functions only add
"nuw" to the generated G_PTR_ADD, but I intend to introduce an
"inbounds" MIFlag in a later PR (analogous to a concurrent effort in
SDAG: #131862, related: #140017, #141725) that will also be set in the
(build|materialize)ObjectPtrOffset functions.

Most test changes just add "nuw" to G_PTR_ADDs. Exceptions are AMDGPU's
call-outgoing-stack-args.ll, flat-scratch.ll, and freeze.ll tests, where
offsets are now folded into scratch instructions, and cases where the
behavior of the check regeneration script changed, resulting, e.g., in
better checks for "nusw G_PTR_ADD" instructions, matched empty lines,
and the use of "CHECK-NEXT" in MIPS tests.

For SWDEV-516125.
2025-07-29 13:04:04 +02:00
paperchalice
21836f4a49
[SelectionDAG] Remove UnsafeFPMath in LegalizeDAG (#146316)
These global flags hinder further improvements like [[RFC] Honor pragmas
with
-ffp-contract=fast](https://discourse.llvm.org/t/rfc-honor-pragmas-with-ffp-contract-fast)
and pass concurrency support. Remove them incrementally.
2025-07-29 08:41:21 +08:00
Ellis Hoag
819f020b28
Use F.hasOptSize() instead of checking optsize directly (#147348) 2025-07-28 08:38:52 -07:00
Abhay Kanhere
33c94450f0
[CodeGen][ARM] Bug fix InsertStackProtectors with EH_SJ_LJ (#147411)
when exception handling with setjmp/longjmp (exception-mode=eh_sjlj is
enabled,
eh_sjlj_callsite intrinsic is inserted in same basic block as the
throwing/exception instruction. This fix ensures stack protector
insertion code does not split the block and move these apart into
different basic blocks.
2025-07-24 10:23:00 -07:00
eleviant
a4796b14fc
[ARM] Emit error message when incompatible reg is specified (#147559)
At the moment the following piece of code causes undefined behavior:
```
int a;
void b() {
   register float d2 asm("d2") = a;
   asm("" ::"r"(d2));
}
```
This happens because variable and register types are incompatible.
2025-07-24 19:19:25 +02:00
Brad Smith
0d2e11f3e8
Remove Native Client support (#133661)
Remove the Native Client support now that it has finally reached end of life.
2025-07-15 13:22:33 -04:00
Trevor Gross
a789b3f381
[test] Add missing tests for Arm frexpf128 and Mips ldexpf128 (#148793)
These platforms have tests for the rest of the float sizes but not
`f128`. Add them here.
2025-07-15 17:35:39 +09:00
Matt Arsenault
3d50e1f3e8
RuntimeLibcalls: Add some tests for OpenBSD stack protectors (#147888)
7dce16f69dc3e26cb74d5ad38b0648a6f47f9640 removed a libcall for
STACKPROTECTOR_CHECK_FAIL from OpenBSD but added no tests.

Add a basic test copied from RISCV into all the backends on
the OpenBSD page of supported architectures before I potentially
break in in RuntimeLibcalls refactoring.
2025-07-15 15:50:54 +09:00
Simon Pilgrim
d8aa4a6721 [ARM][ fp16-promote.ll - cleanup CHECKS to be consistently inside each test. NFC. 2025-07-14 14:41:21 +01:00
AZero13
0edc98cd6d
[ARM] Copy SMAX(lhs, 0) and SMIN(lhs, 0) patterns from AArch64 to ARM (#146565)
They work on ARM too.
2025-07-10 21:06:52 +01:00
Matt Arsenault
d801b54bcd
ARM: Fix calling convention for gnu half conversion functions (#147951)
I'm surprised at how bad the test coverage is here. There is some
overlap with existing tests, but they aren't comprehensive and do
not cover all the ABIs, or all the different types.

Fixes #147935
2025-07-10 22:47:44 +09:00
Matt Arsenault
1e26443cf9
CodeGen: Remove redundant REQUIRES registered-target from backend tests (#147475)
These are already applied to all the tests in the target subdirectory
2025-07-09 09:25:53 +09:00
David Green
9bc3e710fb [ARM][AArch64] Clean up some v3float intrinsic definitions
We have had some v3float definitions sneak in and some functions were
incorrectly named after #146691. Use v3f32 instead.
2025-07-08 07:59:44 +01:00
Jay Foad
17d6aa01ec
[ARM] Fix expansion of ABS in a call sequence (#147270)
Fixes #147162
2025-07-07 15:52:37 +01:00
Matt Arsenault
e7bcd3f7c7 ARM: Remove fast flags from ldexp calls test
These are not relevant to the test, and we should make
sure the calls lower correctly without flags.
2025-07-07 20:01:00 +09:00
Matt Arsenault
465f2b0571
DAG: Fix asserting in error case for frexp softening (#147236) 2025-07-07 18:37:37 +09:00
Matt Arsenault
08defcb6d3
DAG: Fix asserting in error case for powi softening (#147237) 2025-07-07 18:13:11 +09:00
Matt Arsenault
dc5d353f3a
AArch64: Fix some missing llvm.frexp test coverage (#146691)
AArch64 was testing a couple of vector cases, and not the base
scalars. Add the one case that isn't in the ARM version there, and
then copy the rest back into AArch64. Also add a windows run line.
2025-07-07 10:21:44 +09:00
Matt Arsenault
9865d7cb63
ARM: Add missing test coverage for windows frexp libcalls (#146690)
fp128 case crashes, so left off. Also didn't just add to the
other frexp test, since update_llc_test_checks seems to just
ignore this case for some reason, and the other windows tests
are also separated into this subdirectory.
2025-07-07 10:17:53 +09:00
AZero13
7d65cb1952
[ARM] Copy (SELECT_CC setgt, iN lhs, -1, 1, -1) -> (OR (ASR lhs, N-1), 1 from AArch64 to ARM (#146561)
It works perfectly for ARM too.
2025-07-05 18:17:33 +01:00
David Green
9fcea2e465 [ARM] Add neon vector support for roundeven
As per #142559, this marks froundeven as legal for Neon and upgrades the
existing arm.neon.vrintn intrinsics.
2025-07-04 15:27:33 +01:00
David Green
ec35065789 [ARM] Add neon vector support for rint
As per #142559, this marks frint as legal for Neon and upgrades the existing
arm.neon.vrintx intrinsics.
2025-07-03 21:27:48 +01:00
Guy David
76274eb2b3
[PHIElimination] Revert #131837 #146320 #146337 (#146850)
Reverting because mis-compiles:
- https://github.com/llvm/llvm-project/pull/131837
- https://github.com/llvm/llvm-project/pull/146320
- https://github.com/llvm/llvm-project/pull/146337
2025-07-03 07:48:08 -04:00
David Green
1f8f477bd0 [ARM] Add neon vector support for trunc
As per #142559, this marks ftrunc as legal for Neon and upgrades the existing
arm.neon.vrintz intrinsics.
2025-07-03 07:41:13 +01:00
Craig Topper
b62826cc05
[InstrEmitter] Use AddOperand in EmitCopyToRegClassNode. (#146637)
This is alternative to #145965 that allows RegisterSDNode to be handled
without making a special case.
2025-07-02 09:44:54 -07:00
woruyu
bbcebec3af
[DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine (#145298)
This PR resolves https://github.com/llvm/llvm-project/issues/144513

The modification include five pattern :
1.vselect Cond, 0, 0 → 0
2.vselect Cond, -1, 0 → bitcast Cond
3.vselect Cond, -1, x → or Cond, x
4.vselect Cond, x, 0 → and Cond, x
5.vselect Cond, 000..., X -> andn Cond, X

1-4 have been migrated to DAGCombine. 5 still in x86 code.

The reason is that you cannot use the andn instruction directly in
DAGCombine, you can only use and+xor, which will introduce optimization
order issues. For example, in the x86 backend, select Cond, 0, x →
(~Cond) & x, the backend will first check whether the cond node of
(~Cond) is a setcc node. If so, it will modify the comparison operator
of the condition.So the x86 backend cannot complete the optimization of
andn.In short, I think it is a better choice to keep the pattern of
vselect Cond, 000..., X instead of and+xor in combineDAG.

For commit, the first is code changes and x86 test(note 1), the second
is tests in other backend(node 2).

---------

Co-authored-by: Simon Pilgrim <llvm-dev@redking.me.uk>
2025-07-02 15:07:48 +01:00
David Green
5332534b9c [ARM] Add neon vector support for ceil
As per #142559, this marks fceil as legal for Neon and upgrades the existing
arm.neon.vrintp intrinsics.
2025-07-01 15:41:10 +01:00
David Green
6bd9ff04af [ARM] Add neon vector support for round
As per #142559, this marks fround as legal for Neon and upgrades the existing
arm.neon.vrinta intrinsics.
2025-06-30 17:15:26 +01:00
Guy David
f5c62ee0fa
[PHIElimination] Reuse existing COPY in predecessor basic block (#131837)
The insertion point of COPY isn't always optimal and could eventually
lead to a worse block layout, see the regression test in the first
commit.

This change affects many architectures but the amount of total
instructions in the test cases seems too be slightly lower.
2025-06-29 21:28:42 +03:00
David Green
dcc9e36b18
[ARM] Add neon vector support for floor (#142559)
This marks ffloor as legal providing that armv8 and neon is present (or
fullfp16 for the fp16 instructions). The existing arm_neon_vrintm
intrinsics are auto-upgraded to llvm.floor.

If this is OK I will update the other vrint intrinsics.
2025-06-29 11:37:16 +01:00
AZero13
8bd6d36a44
[ARM] Override hasAndNotCompare (#145441)
bics is available on ARM.

USAT regressions are to be fixed after this because that is an issue
with the ARMISelLowering and should be another PR.

Note that opt optimizes those testcases to min/max intrinsics anyway so
this should have no real effect on codegen.

Proof: https://alive2.llvm.org/ce/z/kPVQ3_
2025-06-29 11:15:56 +01:00
Björn Pettersson
237b8de2c0
[IfConversion] Fix bug related to !HasFallThrough (#145471)
We can not trust that !HasFallThrough implies that there is not
fallthrough exit in cases when analyzeBranch failed.

Adding a new blockNeverFallThrough helper to make the tests on
!HasFallThrough safe by also checking IsBrAnalyzable. We also
try to prove no-fallthrough by inspecting the successor list. If
the textual successor isn't in the successor list we know that
there is no fallthrough.

The bug has probably been around for years. Found it when
working on an out-of-tree target.
2025-06-25 09:30:26 +02:00
Bjorn Pettersson
5238f06f72 [IfConversion] Pre-commit testcase for !HasFallThrough bug. NFC
Adding a test case showing that we can't assume that
!HasFallThrough implies that there is no fallthrough exit
in case analyzeBranch returned true (true == "could not analyze").
2025-06-25 09:23:51 +02:00
David Green
888f84f72c
[ARM] Return the correct chain when expanding READ_REGISTER (#145237)
This prevents it CSEing multiple nodes together from "volatile"
registers as they would end up with the same chain. The new chain out
should be the chain from the new READ_REGISTER node.

Fixes #144845
2025-06-25 07:08:46 +01:00
Alex Rønne Petersen
081adc15e8
[Triple][CodeGen] Fix Triple::isTargetEHABICompatible() for NetBSD (#143549)
Even for EABI, NetBSD uses DWARF EH, not EHABI. This change matches the
Clang frontend behavior, and fixes link errors caused by incorrect
references to `__cxa_end_cleanup` rather than `_Unwind_Resume`.

With this change and #143055, I was able to run
[zig-bootstrap](https://github.com/ziglang/zig-bootstrap) to completion
for `arm-netbsd10.1-eabihf`.
2025-06-23 18:49:30 +02:00
Matt Arsenault
48155f93dd
CodeGen: Emit error if getRegisterByName fails (#145194)
This avoids using report_fatal_error and standardizes the error
message in a subset of the error conditions.
2025-06-23 16:33:35 +09:00
David Green
078475d6c1 [ARM] Add test coverage for #144845 and regenerate tests. NFC 2025-06-22 15:24:39 +01:00
Fangrui Song
28bda77843
Introduce MCAsmInfo::UsesSetToEquateSymbol and prefer = to .set
Introduce MCAsmInfo::UsesSetToEquateSymbol to control the preferred
syntax for symbol equating. We now favor the more readable and common
`symbol = expression` syntax over `.set`. This aligns with pre- https://reviews.llvm.org/D44256 behavior.

On Apple platforms, this resolves a clang -S vs -c behavior difference (resolves #104623).

For targets whose = support is unconfirmed, UsesSetToEquateSymbol is set to false.
This also minimizes test updates.

Pull Request: https://github.com/llvm/llvm-project/pull/142289
2025-06-11 22:19:31 -07:00