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4 Commits

Author SHA1 Message Date
zhijian lin
23b3203113
[POWERPC] Fixes an error in the handling of the MTVSRBMI instruction for big-endian (#151565) 
The patch fixed a bug introduced patch [[PowePC] using MTVSRBMI
instruction instead of constant pool in
power10+](https://github.com/llvm/llvm-project/pull/144084#top).

The issue arose because the layout of vector register elements differs
between little-endian and big-endian modes — specifically, the elements
appear in reverse order. This led to incorrect behavior when loading
constants using MTVSRBMI in big-endian configurations.
 2025-08-06 09:36:37 -04:00
zhijian lin
45909ec469
[PowePC] using MTVSRBMI instruction instead of constant pool in power10+ (#144084) 
The instruction MTVSRBMI set 0x00(or 0xFF) to each byte of VSR based on
the bits mask. Using the instruction instead of constant pool can reduce
the asm code size and instructions in power10.
 2025-07-04 10:07:03 -04:00
zhijian lin
ea73fc5f07
[PowerPC] fixed mtvsrbmi.ll test case error caused by run the update_llc_test_checks.py (#144075) 
fixed mtvsrbmi.ll test case error which caused by run the
update_llc_test_checks.py
 2025-06-13 09:38:54 -04:00
zhijian lin
9c2e0bd59c
[PowerPC][NFC] Pre-commit test case for checking whether mtvsrbmi power10 instruction not used (#143956) 
Verify whether the generated assembly for the following function
includes the mtvsrbmi instruction.
 vector unsigned char v00FF()
{
 vector unsigned char x = { 0xFF, 0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0 };
 return x;
 }
 2025-06-13 09:19:10 -04:00