11 Commits

Author SHA1 Message Date
Matt Arsenault
cccb4fc4b8
AMDGPU: Test more types with minimumnum and maximumnum (#139242)
We had custom lowering for the wider vectors of f16, but missing
test coverage for them. Also add more vector tests for bf16, and
split the bf16 cases into separate files so we can add globalisel
run lines.
2025-05-09 20:29:14 +02:00
Matt Arsenault
e4751d5cbc
AMDGPU: Add minimumnum/maximumnum tests with amdgpu-ieee=0 (#139145)
With the IEEE bit disabled, the hardware instructions have the
same behavior as these operations.
2025-05-09 08:17:49 +02:00
Matt Arsenault
6cf84e036e
AMDGPU: Test more subtargets in minimumnum/maximumnum tests (#139144) 2025-05-09 08:15:09 +02:00
Brox Chen
6dbc01e801
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)
This is a NFC patch.

This patch run a bulk update on CodeGen tests that are impacted by the
true16 features. This patch applies:
1. duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16"
2. update the test with the update script

For some GISEL runlines, the current CodeGen do not fully support the
true16 version. Still update the runlines, but comment out the failing
one, and added a "FIXME-TRUE16" comment to that test for easier
tracking. These test will be fixed in the following patches.

This is in a transition state that we support both
"+real-true16/-real-true16" in our code base. We plan to move to
"+real-true16" as default, and finally remove "-real-true16" mode and
test lines.
2025-04-23 13:06:52 -04:00
Carl Ritson
a3a3e6997b
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
- Algorithm operates over whole IR to attempt to minimize waits.
- Add support for VALU->VALU SGPR hazards via VA_SDST/VA_VCC.
2025-01-30 11:21:11 +09:00
Phoebe Wang
1547382033
[X86] Support lowering of FMINIMUMNUM/FMAXIMUMNUM (#121464) 2025-01-06 21:28:58 +08:00
Shilei Tian
6548b6354d Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
2024-11-08 20:21:16 -05:00
Shilei Tian
ca33649abe Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.
2024-11-08 16:36:35 -05:00
Shilei Tian
e215a1e27d
[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403) 2024-11-08 13:05:35 -05:00
Matt Arsenault
5883ad34d6
DAG: Handle vector legalization of minimumnum/maximumnum (#109779)
Follow the same patterns as the other min/max variants.
2024-09-30 13:43:35 +04:00
Matt Arsenault
ee61a4db3c AMDGPU: Add tests for minimumnum/maximumnum intrinsics
Vector cases are broken, so leave those for later.
2024-09-11 18:20:03 +04:00