31813 Commits

Author SHA1 Message Date
Ramkumar Ramachandra
c807395011
[LAA/SLP] Don't truncate APInt in getPointersDiff (#139941)
Change getPointersDiff to return an std::optional<int64_t>, and fill
this value with using APInt::trySExtValue. This simple change requires
changes to other functions in LAA, and major changes in SLPVectorizer
changing types from 32-bit to 64-bit.

Fixes #139202.
2025-05-15 10:08:05 +01:00
Madhur Amilkanthwar
40778822f7
[GVN][NFC] Add MSSA checks in tests 2/N (#137814)
The previous patch in this series is #130261
2025-05-15 10:29:41 +05:30
Jessica Clarke
864f0ff4ef
[clang][IR] Overload @llvm.thread.pointer to support non-AS0 targets (#132489)
Thread-local globals live, by default, in the default globals address
space, which may not be 0, so we need to overload @llvm.thread.pointer
to support other address spaces, and use the default globals address
space in Clang.
2025-05-14 21:51:56 +01:00
Min-Yih Hsu
0ab67ec191
[LV][EVL] Introduce the EVLIndVarSimplify Pass for EVL-vectorized loops (#131005)
When we enable EVL-based loop vectorization w/ predicated tail-folding,
each vectorized loop has effectively two induction variables: one
calculates the step using (VF x vscale) and the other one increases the
IV by values returned from experiment.get.vector.length. The former,
also known as canonical IV, is more favorable for analyses as it's
"countable" in the sense of SCEV; the latter (EVL-based IV), however, is
more favorable to codegen, at least for those that support scalable
vectors like AArch64 SVE and RISC-V.

The idea is that we use canonical IV all the way until the end of all
vectorizers, where we replace it with EVL-based IV using EVLIVSimplify
introduced here. Such that we can have the best from both worlds.

This Pass is enabled by default in RISC-V. However, since we haven't
really vectorize loops with predicate tail-folding by default, this Pass
is no-op at this moment.
2025-05-14 13:49:50 -07:00
Yingwei Zheng
aa054c6810
[ConstraintElim] Simplify and/or instead of replacing its operand (#139874)
In `checkOrAndOpImpliedByOther`, replacing an operand of a disjoint or
is unsafe: https://alive2.llvm.org/ce/z/4R4hxN
This patch performs the simplification directly, to avoid miscompilation
and unnecessary canonicalization.

Closes https://github.com/llvm/llvm-project/issues/137937.
2025-05-14 23:37:41 +08:00
Alexey Bataev
c632ac3506 [SLP][NFC]Add a test with the gather operand in phi node in gathered loads 2025-05-14 08:18:23 -07:00
Florian Hahn
7a9fd62278
[VPlan] Use VPlan operand order for VPBlendRecipes. (#139475)
Don't use the order of incoming values of IR phis when creating 
VPBlendRecipes. Instead, simply use the incoming operands and
blocks from the VPWidenPHIRecipe.

Note that this changes the order of the incoming operands/masks for some
blends.

PR: https://github.com/llvm/llvm-project/pull/139475
2025-05-14 14:56:35 +01:00
Marina Taylor
1914184e5c
Reland "[ObjCARC][Contract] Optimize bundled RetainRV to ClaimRV" (#139889)
This teaches ObjCARCContract to transform attachedcall bundles
referencing objc_retainAutoreleasedReturnValue to instead reference
objc_claimAutoreleasedReturnValue.

The only distinction between the two is that the latter is required to
be guaranteed to immediately follow the call it's attached to, and, by
construction, the bundles always achieve that by:
- not being separable from the call through IR and the backend
- not getting the marker emitted when claimARV is the attachedcall.

This is enabled only for arm64, arm64e, and arm64_32 on macOS13/iOS16
and related operating systems.

Co-authored-by: Ahmed Bougacha <ahmed@bougacha.org>
2025-05-14 14:21:52 +01:00
Usman Nadeem
b93173185d
[InstCombine] Narrow trunc(lshr) in more cases (#139645)
We can narrow `trunc(lshr(i32)) to i8` to `trunc(lshr(i16)) to i8` even
when the bits that we are shifting in are not zero, in the cases where
the MSBs of the shifted value don't actually matter and actually end up
being truncated away.

This kind of narrowing does not remove the trunc but can help the
vectorizer generate better code in a smaller type.
Motivation: libyuv, functions like ARGBToUV444Row_C().

Proof: https://alive2.llvm.org/ce/z/9Ao2aJ
2025-05-13 13:42:42 -07:00
Drew Kersnar
a1e1a84d2c
[NVPTX] Vectorize and lower 256-bit global loads/stores for sm_100+/ptx88+ (#139292)
PTX 8.8+ introduces 256-bit-wide vector loads/stores under certain
conditions. This change extends the backend to lower these loads/stores.
It also overrides getLoadStoreVecRegBitWidth for NVPTX, allowing the
LoadStoreVectorizer to create these wider vector operations.

See the spec for the three relevant PTX instructions here:
- https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-ld
- https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-ld-global-nc
- https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-st
2025-05-13 13:36:09 -07:00
Marina Taylor
5bb8e9db5f
Revert "[ObjCARC][Contract] Optimize bundled RetainRV to ClaimRV" (#139780)
Reverts llvm/llvm-project#139762 for breaking bots
2025-05-13 20:20:06 +01:00
PiJoules
649b7994fb
[NFC][WPD] Add constant propagation tests checking relative vtables (#138989)
This is a patch with precommitted tests to make
https://github.com/llvm/llvm-project/pull/136630 easier to review. The
`virtual-const-prop-small-alignment-*` tests check the output when the
loaded int alignment is less than the vtable alignment.

This also changes some constants to make it easier to differentiate
between propagated values in vtables.
2025-05-13 11:50:11 -07:00
Marina Taylor
810148cb07
[ObjCARC][Contract] Optimize bundled RetainRV to ClaimRV (#139762)
This teaches ObjCARCContract to transform attachedcall bundles
referencing objc_retainAutoreleasedReturnValue to instead reference
objc_claimAutoreleasedReturnValue.

The only distinction between the two is that the latter is required to
be guaranteed to immediately follow the call it's attached to, and, by
construction, the bundles always achieve that by:
- not being separable from the call through IR and the backend
- not getting the marker emitted when claimARV is the attachedcall.

This is enabled only for arm64, arm64e, and arm64_32 on macOS13/iOS16
and related operating systems.

Co-authored-by: Ahmed Bougacha <ahmed@bougacha.org>
2025-05-13 19:25:28 +01:00
Luke Lau
55c48ee6f1
[RISCV] Ignore interleaved accesses with non-default address spaces (#139698)
This fixes a crash introduced in
https://github.com/llvm/llvm-project/pull/137045#issuecomment-2872208568
where we don't have overloaded pointer types for segmented load/store
intrinsics.

This should be temporary until #139634 lands and overloads the pointer
type for these
2025-05-13 14:40:16 +01:00
Ryotaro Kasuga
e99ca74dc1
[LoopInterchange] Relax the legality check to accept more patterns (#139690)
When proving the legality of exchanging two loops, it doesn't need to
check the elements of the direction vectors associated with the loops
outside of the two target loops. Before this patch, the legality check
looked at all elements of a direction vector to calculate the
lexicographically order of the vector, which may reject some legal
exchanges. For example, if a direction vector is `[* < =]`, it is safe
to swap the last two loops because the corresponding subsequence of the
vector (`[< =]`) is lexicographically positive for both before and after
the exchange. However, the its order is unknown if we don't drop the
prefix since the first element is `*`. This patch improves the logic of
legality check to ignore such unrelated prefixes of direction vectors.
2025-05-13 21:14:14 +09:00
Pierre van Houtryve
2278f5e65b
[AMDGPU] Hoist readlane/readfirstlane through unary/binary operands (#129037)
When a read(first)lane is used on a binary operator and the intrinsic is
the only user of the operator, we can move the read(first)lane into the
operand if the other operand is uniform.

Unfortunately IC doesn't let us access UniformityAnalysis and thus we
can't truly check uniformity, we have to do with a basic uniformity
check which only allows constants or trivially uniform intrinsics calls.

We can also do the same for unary and cast operators.
2025-05-13 12:00:49 +02:00
David Green
671cef029f
[AggressiveInstcombine] Fold away shift in or reduction chain. (#137875)
If we have `icmp eq or(a, shl(b)), 0` then the shift can be removed so
long as it is nuw or nsw. It is still comparing that some bits are
non-zero.
https://alive2.llvm.org/ce/z/nhrBVX.

This is also true of ne, and true for longer or chains.
2025-05-13 10:33:38 +01:00
Matt Arsenault
6d35ec2335
ObjCARC: Fix regression from using ConstantData uselists (#139609)
Fixes regression after 9383fb23e18bb983d0024fb956a0a724ef9eb03d
2025-05-13 10:52:49 +02:00
Antonio Frighetto
adfd59fdb8 [InstCombine] Introduce foldICmpBinOpWithConstantViaTruthTable folding
Match icmps of binops where both operands are select with constant arms,
i.e., `icmp pred (select A ? C1 : C2) binop (select B ? C3 : C4), C5`.
Fold such patterns by creating a truth table of the possible four
constant variants, and materialize back the optimal logic from it via
`createLogicFromTable` helper. This also generalizes an existing fold,
which has therefore been dropped.

Proofs: https://alive2.llvm.org/ce/z/NS7Vzu.

Fixes: https://github.com/llvm/llvm-project/issues/138212.
2025-05-13 09:04:25 +02:00
Antonio Frighetto
1bfd94b1b9 [InstCombine] Precommit tests for PR139109 (NFC) 2025-05-13 09:03:56 +02:00
Yingwei Zheng
6f1f6d184f
[InstCombine][DebugInfo] Update debug value uses in freelyInvertAllUsersOf (#137013)
This patch updates all debug value uses in `freelyInvertAllUsersOf` by
inserting `DW_OP_not` at the front of the DIExpression.

Related issue: https://github.com/llvm/llvm-project/issues/71065
2025-05-13 08:56:22 +08:00
Luke Lau
cf3242f3b0
[InstCombine] Pull shuffles out of binops with splatted ops (#137948)
Given a binary op on splatted vector and a splatted constant,
InstCombine will normally pull the shuffle out in
`InstCombinerImpl::foldVectorBinop`:

```llvm
define <4 x i32> @f(i32 %x) {
  %x.insert = insertelement <4 x i32> poison, i32 %x, i64 0
  %x.splat = shufflevector <4 x i32> %x.insert, <4 x i32> poison, <4 x i32> zeroinitializer
  %res = add <4 x i32> %x.splat, splat (i32 42)
  ret <4 x i32> %res
}
```

```llvm
define <4 x i32> @f(i32 %x) {
  %x.insert = insertelement <4 x i32> poison, i32 %x, i64 0
  %1 = add <4 x i32> %x.insert, <i32 42, i32 poison, i32 poison, i32 poison>
  %res = shufflevector <4 x i32> %1, <4 x i32> poison, <4 x i32> zeroinitializer
  ret <4 x i32> %res
}
```

However, this currently only operates on fixed length vectors. Splats of
scalable vectors don't currently have their shuffle pulled out, e.g:

```llvm
define <vscale x 4 x i32> @f(i32 %x) {
  %x.insert = insertelement <vscale x 4 x i32> poison, i32 %x, i64 0
  %x.splat = shufflevector <vscale x 4 x i32> %x.insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
  %res = add <vscale x 4 x i32> %x.splat, splat (i32 42)
  ret <vscale x 4 x i32> %res
}
```

Having this canonical form with the shuffle pulled out is important as
VectorCombine relies on it in order to scalarize binary ops in
`scalarizeBinopOrCmp`, which would prevent the need for #137786. This
also brings it in line for scalable binary ops with two non-constant
operands: https://godbolt.org/z/M9f7ebzca

This adds a combine just after the fixed-length version, but restricted
to splats at index 0 so that it also handles the scalable case:

So the whilst the existing combine looks like: `Op(shuffle(V1, Mask), C)
-> shuffle(Op(V1, NewC), Mask)`

This patch adds: `Op(shuffle(V1, 0), (splat C)) -> shuffle(Op(V1, (splat
C)), 0)`

I think this could be generalized to other splat indexes that aren't
zero, but I think it would be dead code since only fixed-length vectors
can have non-zero shuffle indices, which would be covered by the
existing combine.
2025-05-13 00:11:55 +01:00
Ellis Hoag
78f0af5d89
[SimplifyCFG][swifterror] Don't sink calls with swifterror params (#139015)
We've encountered an LLVM verification failure when building Swift with
the SimplifyCFG pass enabled. I found that
https://reviews.llvm.org/D158083 fixed this pass by preventing sinking
loads or stores of swifterror values, but it did not implement the same
protection for call or invokes.
In `Verifier.cpp`
[here](c685355811/llvm/lib/IR/Verifier.cpp (L4360-L4364))
and
[here](c685355811/llvm/lib/IR/Verifier.cpp (L3661-L3662))
we can see that swifterror values must also be used directly by call
instructions.
2025-05-12 14:37:26 -07:00
Alexey Bataev
e1ea86e849 [SLP]Do not try to use interleaved loads, if reordering is required
If the interleaved loads require reordering, better to avoid generate
load + shuffle sequence, which in this case cannot be recognized as
interleaved load. Also, it fixes the issue with the incorrect codegen.

Fixes #138923
2025-05-12 14:12:51 -07:00
Alexey Bataev
fa985b5f1e [SLP][NFC]Add a test with missed reordering of the interleaved loads 2025-05-12 13:48:11 -07:00
Matt Arsenault
038d357dde
AMDGPU: Use minimumnum/maximumnum for fmed3 with amdgpu-ieee=0
(#139546)

Try to respect the signaling nan behavior of the instruction,
so also start the special case fold for src2.
2025-05-12 20:31:52 +02:00
Matt Arsenault
08dd0406c6
AMDGPU: Use minnum instead of maxnum for fmed3 src2-nan fold (#139531)
By the pseudocode in the ISA manual, if any input is a nan it acts
like min3, which will fold to min2 of the other operands. The other
cases fold to min, I'm not sure how this one was wrong.
2025-05-12 20:26:29 +02:00
Matt Arsenault
83107e02ea
AMDGPU: Disable most fmed3 folds for strictfp (#139530) 2025-05-12 20:21:02 +02:00
Matt Arsenault
e805d83487
AMDGPU: Add more tests for fmed3 instcombine folds (#139529)
Add test with snan literals, and test with and without amdgpu-ieee
2025-05-12 20:18:07 +02:00
Florian Hahn
d39ca81fdd
[LoopPeel] Add initial tests for peeling the last iteration.
Precommit tests for upcoming PR.
2025-05-12 14:56:21 +01:00
Alexey Bataev
2e13f7ab01 [SLP][NFC]Add a test with the incorrect vectorization for the pointers with distance difference > 2^32 2025-05-12 06:30:05 -07:00
Han-Kuan Chen
53df6400af
[SLP] Fix incorrect operand order in interchangeable instruction. (#139225) 2025-05-12 20:03:45 +08:00
John Brawn
7d867c6d09
[LoopVersioningLICM] Only mark pointers with generated checks as noalias (#135168)
Currently when we version a loop all loads and stores have the noalias
metadata added to them. If there were some pointers that could not be
analysed, and thus we could not generate runtime aliasing checks for,
then we should not mark loads and stores using these pointers as
noalias.

This is done by getting rid of setNoAliasToLoop and instead using
annotateLoopWithNoAlias, as that already correctly handles partial alias
information. This does result in slightly different aliasing metadata
being generated, but it looks like it's more precise.

Currently this doesn't result in any change to the transforms that
LoopVersioningLICM does, as LoopAccessAnalysis discards all results if
it couldn't analyse every pointer leading to no loop versioning
happening, but an upcoming patch will change that and we need this first
otherwise we incorrectly mark some pointers as noalias even when they
aren't.
2025-05-12 10:15:22 +01:00
Simon Pilgrim
63f3a5babd [PhaseOrdering][X86] Add test coverage for #48223
The X86 backend shuffle combining is saving us from some poor vectorised IR
2025-05-12 09:16:13 +01:00
Matt Arsenault
4b89339899
AMDGPU: Reorganize fmed3 intrinsic instcombine tests (#139498) 2025-05-12 10:05:03 +02:00
Shan Huang
5971b41919
[DebugInfo][LICM] Salvage dbg_values for the dead instructions to erase (#138796)
fix #138684 .
2025-05-12 09:07:30 +08:00
Shan Huang
86ceed7112
[DebugInfo][LoopDistribute] Salvage debug values using dead instructions in the distributed loops (#137124)
Fix #136532 .
2025-05-12 09:06:42 +08:00
Alexey Bataev
49042f2bee [SLP][NFC]Add a test with ordering of the operands of unordered loads 2025-05-11 08:09:51 -07:00
Alex MacLean
369891b674
[NVPTX] use untyped loads and stores where ever possible (#137698)
In most cases, the type information attached to load and store
instructions is meaningless and inconsistently applied. We can usually
use ".b" loads and avoid the complexity of trying to assign the correct
type. The one expectation is sign-extending load, which will continue to
use ".s" to ensure the sign extension into a larger register is done
correctly.
2025-05-10 08:26:26 -07:00
Florian Hahn
5fa64d65e9
[VPlan] Use printPhiOperands for VPPhi.
Split off from  https://github.com/llvm/llvm-project/pull/139151 to land
printing improvements separately.

Updates printing of VPPhi operands to be consistent with
VPWidenPHIRecipe.
2025-05-10 12:49:29 +01:00
Alexander Richardson
2d2d753e01
[AtomicExpand] Drop explicit datalayout from test
Also remove the R600 checks this test as well as a duplicate RUN line.

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/137923
2025-05-09 19:43:26 -07:00
Teresa Johnson
8836d68a0d
[MemProf] Optionally discard small non-cold contexts (#139113)
Adds a new option -memprof-callsite-cold-threshold that allows
specifying a percent that will cause non-cold contexts to be discarded
if the percent cold bytes at a callsite including that context exceeds
the given threshold. Default is 100% (no discarding).

This reduces the amount of cloning needed to expose cold allocation
contexts when parts of the context are dominantly cold.

This motivated the change in PR138792, since discarding a context might
require a different decision about which not-cold contexts must be kept
to expose cloning requirements, so we need to determine that on the fly.

Additionally, this required a change to include the context size
information in the alloc trie in more cases, so we now guard the
inclusion of this information in the generated metadata on the option
values.
2025-05-09 15:56:54 -07:00
Daniel Paoliello
97a58b04c6
[aarch64][x86][win] Add compiler support for MSVC's /funcoverride flag (Windows kernel loader replaceable functions) (#125320)
Adds support for MSVC's undocumented `/funcoverride` flag, which marks
functions as being replaceable by the Windows kernel loader. This is
used to allow functions to be upgraded depending on the capabilities of
the current processor (e.g., the kernel can be built with the naive
implementation of a function, but that function can be replaced at boot
with one that uses SIMD instructions if the processor supports them).

For each marked function we need to generate:
* An undefined symbol named `<name>_$fo$`.
* A defined symbol `<name>_$fo_default$` that points to the `.data`
section (anywhere in the data section, it is assumed to be zero sized).
* An `/ALTERNATENAME` linker directive that points from `<name>_$fo$` to
`<name>_$fo_default$`.

This is used by the MSVC linker to generate the appropriate metadata in
the Dynamic Value Relocation Table.

Marked function must never be inlined (otherwise those inline sites
can't be replaced).

Note that I've chosen to implement this in AsmPrinter as there was no
way to create a `GlobalVariable` for `<name>_$fo$` that would result in
a symbol being emitted (as nothing consumes it and it has no
initializer). I tried to have `llvm.used` and `llvm.compiler.used` point
to it, but this didn't help.

Within LLVM I referred to this feature as "loader replaceable" as
"function override" already has a different meaning to C++ developers...

I also took the opportunity to extract the feature symbol generation
code used by both AArch64 and X86 into a common function in AsmPrinter.
2025-05-09 14:56:38 -07:00
David Green
3b4d5638b3 [AArch64] Limit vector splitting to vectors of size larger than 128bit
The intent of this code is to split larger vectors into smaller shuffles, but
it currently triggering on some small vector types. Limit it to vectors of size
>128bit.
2025-05-09 22:17:28 +01:00
Florian Hahn
8c6c525a6b
[LV] Don't consider FORs as profitable to scalarize.
Fixed-order recurrence phis cannot be scalarized, they will always be
widened at the moment. Make sure they are not incorrectly considered
profitable to scalarize, similar to 41c1a7be3f1a2556e.

Fixes https://github.com/llvm/llvm-project/issues/139060.
Fixes https://github.com/llvm/llvm-project/issues/139065.
2025-05-09 20:29:22 +01:00
Emma Pilkington
7babf22461
[StructurizeCFG] Stop setting DebugLocs in flow blocks (#139088)
Flow blocks are generated code that don't really correspond to any
location in the source, so principally they should have empty DebugLocs.
Practically, setting these debug locs leads to redundant is_stmts being
generated after #108251, causing stepping test failures in the ROCm GDB
test suite.

Fixes SWDEV-502134
2025-05-09 14:22:14 -04:00
Gheorghe-Teodor Bercea
25a031947a
[AMDGPU][NFC] Add tests in preparation for i8 vectorization (#138801)
Precommit tests for PR: https://github.com/llvm/llvm-project/pull/134934
2025-05-09 10:32:49 -04:00
Ramkumar Ramachandra
f058333941
[LV] Regen a test with UTC (#139235) 2025-05-09 14:26:20 +01:00
Florian Hahn
e854c381c6
[VPlan] Manage noalias/alias_scope metadata in VPlan. (#136450)
Use VPIRMetadata added in
https://github.com/llvm/llvm-project/pull/135272
to also manage no-alias metadata added by versioning.

Note that this means we have to build the no-alias metadata up-front
once. If it is not used, it will be discarded automatically.

This also fixes a case where incorrect metadata was added to wide
loads/stores that got converted from an interleave group.

Compile-time impact is neutral:

https://llvm-compile-time-tracker.com/compare.php?from=38bf1af41c5425a552a53feb13c71d82873f1c18&to=2fd7844cfdf5ec0f1c2ce0b9b3ae0763245b6922&stat=instructions:u
2025-05-09 11:19:12 +01:00
David Green
76b3adabea [AggressiveInstCombine] Add test for shifts from or chains. NFC 2025-05-09 09:29:50 +01:00