Jia Liu
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b22310fda6
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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
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2012-02-18 12:03:15 +00:00 |
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Tanya Lattner
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48b182c3a4
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In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
Updated test case and reverted change to the PerfectShuffle Table.
llvm-svn: 131529
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2011-05-18 06:42:21 +00:00 |
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Tanya Lattner
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c7e291b354
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vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
llvm-svn: 131488
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2011-05-17 20:48:40 +00:00 |
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Jim Grosbach
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1f2b4bdb22
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Regenerate. No functional change, just cleanup.
llvm-svn: 116459
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2010-10-14 00:15:18 +00:00 |
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Anton Korobeynikov
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a3090655d5
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Regenerate
llvm-svn: 82814
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2009-09-25 22:53:17 +00:00 |
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Anton Korobeynikov
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9a232f46a8
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Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table.
llvm-svn: 79624
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2009-08-21 12:41:24 +00:00 |
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