5 Commits

Author SHA1 Message Date
Krzysztof Drewniak
3f2e3e67c1
[mlir][AMDGPU][NFC] Fix overlapping masked load refinements (#159805)
The two paterns for handlig vector.maskedload on AMD GPUs had an overlap
- both the "scalar mask becomes an if statement" pattern and the "masked
loads become a normal load + a select on buffers" patterns could handle
a load with a broadcast mask on a fat buffer resource.

This commet add checks to resolve the overlap.
2025-12-02 11:02:45 -08:00
Maksim Levental
967626b842
[mlir][NFC] update mlir/Dialect create APIs (14/n) (#149920)
See https://github.com/llvm/llvm-project/pull/147168 for more info.
2025-07-24 13:03:47 -05:00
Kazu Hirata
0925d7572a
[mlir] Remove unused includes (NFC) (#150266)
These are identified by misc-include-cleaner.  I've filtered out those
that break builds.  Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.
2025-07-23 15:18:53 -07:00
Kunwar Grover
f96492221d
[mlir][AMDGPU] Add better load/store lowering for full mask (#146748)
This patch adds a better maskedload/maskedstore lowering on amdgpu
backend for loads which are either fully masked or fully unmasked. For
these cases, we can either generate a oob buffer load with no if
condition, or we can generate a normal load with a if condition (if no
fat_raw_buffer space).
2025-07-10 16:11:19 +01:00
Zhuoran Yin
6a97b56ce5
[MLIR][AMDGPU] Redirect transfer read to masked load lowering (#146705)
This PR reworks https://github.com/llvm/llvm-project/pull/131803.
Instead of applying the optimization on transfer_read op, which is too
high level, it redirect the pre-existing pattern onto maskedload op.
This simplified the implementation of the lowering pattern. This also
allows moving the usage of the pass to a target dependent pipeline.

Signed-off-by: jerryyin <zhuoryin@amd.com>
2025-07-02 18:24:44 +01:00