5270 Commits

Author SHA1 Message Date
Simon Pilgrim
86779da52b
[VectorCombine] Fold "(or (zext (bitcast X)), (shl (zext (bitcast Y)), C))" -> "(bitcast (concat X, Y))" MOVMSK bool mask style patterns (#119695)
Mask/Bool vectors are often bitcast to/from scalar integers, in particular when concatenating mask results, often this is due to the difficulties of working with vector of bools on C/C++. On x86 this typically involves the MOVMSK/KMOV instructions.

To concatenate bool masks, these are typically cast to scalars, which are then zero-extended, shifted and OR'd together.

This patch attempts to match these scalar concatenation patterns and convert them to vector shuffles instead. This in turn often assists with further vector combines, depending on the cost model.

Reapplied patch from #119559 - fixed use after free issue.

Fixes #111431
2024-12-12 13:45:10 +00:00
Florian Hahn
a480d51722
[VPlan] Use existing vector trip count VPValue for resume phi (NFC)
Instead of going through getOrAddLiveIn to get a VPValue for the vector
trip count retrieve it directly from VPlan via getVectorTripCount.

Small simplification following 0e70289f373.
2024-12-12 11:03:47 +00:00
Simon Pilgrim
b604d23feb [VectorCombine] Pull out isa<VectorType> check.
Noticed while investigating a crash in #119559 - we don't account for I being replaced and its Type being reallocated. So hoist the checks to the start of the loop.
2024-12-12 11:02:01 +00:00
Mel Chen
b3cba9be41
[LoopVectorize] Vectorize select-cmp reduction pattern for increasing integer induction variable (#67812)
Consider the following loop:
```
  int rdx = init;
  for (int i = 0; i < n; ++i)
    rdx = (a[i] > b[i]) ? i : rdx;
```
We can vectorize this loop if `i` is an increasing induction variable.
The final reduced value will be the maximum of `i` that the condition
`a[i] > b[i]` is satisfied, or the start value `init`.

This patch added new RecurKind enums - IFindLastIV and FFindLastIV.

---------

Co-authored-by: Alexey Bataev <5361294+alexey-bataev@users.noreply.github.com>
2024-12-12 16:48:31 +08:00
Luke Lau
b26fe5b7e9
[VPlan] Use variadic isa<> in a few more places. NFC (#119538) 2024-12-12 13:26:39 +08:00
Michal Paszkowski
04313b86a5
Revert "[LoadStoreVectorizer] Postprocess and merge equivalence classes" (#119657)
Reverts llvm/llvm-project#114501, due to the following failure:
https://lab.llvm.org/buildbot/#/builders/55/builds/4171
2024-12-11 20:36:23 -08:00
Vyacheslav Klochkov
fd2f8d485d
[LoadStoreVectorizer] Postprocess and merge equivalence classes (#114501)
This patch introduces a new method:
void Vectorizer::mergeEquivalenceClasses(EquivalenceClassMap &EQClasses)
const

The method is called at the end of
Vectorizer::collectEquivalenceClasses() and is needed to merge
equivalence classes that differ only by their underlying objects (UO1
and UO2), where UO1 is 1-level-indirection underlying base for UO2. This
situation arises due to the limited lookup depth used during the search
of underlying bases with llvm::getUnderlyingObject(ptr).

Using any fixed lookup depth can result into creation of multiple
equivalence classes that only differ by 1-level indirection bases.

The new approach merges equivalence classes if they have adjacent bases
(1-level indirection). If a series of equivalence classes form ladder
formed of 1-step/level indirections, they are all merged into a single
equivalence class. This provides more opportunities for the load-store
vectorizer to generate better vectors.

---------

Signed-off-by: Klochkov, Vyacheslav N <vyacheslav.n.klochkov@intel.com>
2024-12-11 19:01:35 -08:00
Florian Hahn
5fae408d3a
[VPlan] Dispatch to multiple exit blocks via middle blocks. (#112138)
A more lightweight variant of
https://github.com/llvm/llvm-project/pull/109193,
which dispatches to multiple exit blocks via the middle blocks.

The patch also introduces a bit of required scaffolding to enable
early-exit vectorization, including an option. At the moment, early-exit
vectorization doesn't come with legality checks, and is only used if the
option is provided and the loop has metadata forcing vectorization. This
is only intended to be used for testing during bring-up, with @david-arm
enabling auto early-exit vectorization plugging in the changes from
https://github.com/llvm/llvm-project/pull/88385.

PR: https://github.com/llvm/llvm-project/pull/112138
2024-12-11 21:11:05 +00:00
Vitaly Buka
89b7aea573
Revert "[VectorCombine] Fold "(or (zext (bitcast X)), (shl (zext (bitcast Y)), C))" -> "(bitcast (concat X, Y))" MOVMSK bool mask style patterns" (#119594)
Reverts llvm/llvm-project#119559

Introduce use after free, see llvm/llvm-project#119559
2024-12-11 10:50:26 -08:00
Simon Pilgrim
08f904011f
[VectorCombine] Fold "(or (zext (bitcast X)), (shl (zext (bitcast Y)), C))" -> "(bitcast (concat X, Y))" MOVMSK bool mask style patterns (#119559)
Mask/Bool vectors are often bitcast to/from scalar integers, in particular when concatenating mask results, often this is due to the difficulties of working with vector of bools on C/C++. On x86 this typically involves the MOVMSK/KMOV instructions.

To concatenate bool masks, these are typically cast to scalars, which are then zero-extended, shifted and OR'd together.

This patch attempts to match these scalar concatenation patterns and convert them to vector shuffles instead. This in turn often assists with further vector combines, depending on the cost model.

Fixes #111431
2024-12-11 16:40:56 +00:00
Simon Pilgrim
673c324ae3 [VectorCombine] foldInsExtVectorToShuffle - canonicalize new shuffle(undef,x) -> shuffle(x,undef).
foldInsExtVectorToShuffle is likely to be inserting into an undef value, so make sure we've canonicalized this to the RHS in the folded shuffle to help further VectorCombine folds.

Minor tweak to help #34072
2024-12-11 16:09:13 +00:00
Han-Kuan Chen
51a0c1bf25
[SLP] NFC. Replace TreeEntry::setOperandsInOrder with VLOperands. (#118949)
To reduce repeated code, TreeEntry::setOperandsInOrder will be replaced
by VLOperands.
Arg_size will be provided to make sure other operands will not be
reorderd when VL[0] is IntrinsicInst (because APO is a boolean value).
In addition, BoUpSLP::reorderInputsAccordingToOpcode will also be
removed since it is simple.
2024-12-11 10:09:23 +08:00
LiqinWeng
b759020cc8
[LV][EVL] Support cast instruction with EVL-vectorization (#108351) 2024-12-11 10:01:41 +08:00
vporpo
cafb6b99bb
[SandboxVec][DAG] Update MemDGNode chain upon instr deletion (#118921) 2024-12-10 15:10:45 -08:00
Alexey Bataev
a42aa8f265 [SLP]Fix adjusting of the mask for the fully matched nodes.
When checking for the poison elements in the matches node, need to
consider the register number, when clearing the corresponding mask
element.

Fixes #119393
2024-12-10 09:47:16 -08:00
Han-Kuan Chen
da421f55a7
[SLP] NFC. Make InstructionsState more constant. (#118609)
Add getMainOp and getAltOp.
Use `InstructionsState &` instead of `const InstructionsState &`.
Use `!S.isAltShuffle()` instead of `S.MainOp == S.AltOp`.
2024-12-10 23:28:14 +08:00
Simon Pilgrim
05b907f66b
[VectorCombine] foldShuffleOfShuffles - allow fold with only single shuffle operand. (#119354)
foldShuffleOfShuffles already handles "shuffle (shuffle x, undef), (shuffle y, undef)" patterns, this patch relaxes the requirement so it can handle cases where only a single operand is a shuffle (and the other can be any other value and will be kept in place).

Fixes #86068
2024-12-10 13:10:25 +00:00
Han-Kuan Chen
b97c447dac
[SLP] NFC. Add assert for shouldBroadcast and canBeVectorized. (#119327) 2024-12-10 19:25:19 +08:00
Florian Hahn
0e7f18791c
[LV] Relax assertion in fixupIVUsers (NFC).
Adjust the assertion in fixupIVUsers to only require a unique exit block
if there are any values to fix up. This enables the bring up of
multi-exit loop vectorization without requiring a scalar epilogue.

Split off as suggested from
https://github.com/llvm/llvm-project/pull/112138.
2024-12-10 10:39:28 +00:00
Florian Hahn
56ddbeff83
[LV] Use getUniqueLatchExitBlock in createVectorLoopSkeleton (NFC).
Use getUniqueLatchExitBlock instead of getUniqueExitBlock in preparation
for multi-exit vectorization *without* requiring a scalar epilogue.

Split off as suggested from
https://github.com/llvm/llvm-project/pull/112138
2024-12-10 09:35:08 +00:00
Florian Hahn
e9834209aa
[VPlan] Move convertToConreteRecipes to end of VPlan-opt phase (NFCI).
Adjust placement as suggested in
https://github.com/llvm/llvm-project/pull/114305, after some refactoring
to prepare for the move.
2024-12-10 09:13:13 +00:00
Florian Hahn
0e70289f37
[VPlan] Create canonical IV resume value for epilogue in VPlan. (NFCI)
Update the code to create induction resume PHIs to also create a resume
phi for the canonical induction during epilogue vectorization. This
unifies the code for handling induction resume values and removes the
need to explicitly create manually resume PHI and return it during
epilogue creation.

Overall it helps to move the code for updating the canonical induction
resume value to the place where all other header phi resume values are
updated.

This is NFC, modulo order of the created phis.
2024-12-09 23:11:38 +00:00
Florian Hahn
adfe54f7da
[VPlan] Directly check VectorizingEpilogue in ::executePlan (NFC).
Directly check VectorizingEpilogue which directly indicates that the
epilogue is vectorized.
2024-12-09 22:21:25 +00:00
Florian Hahn
4fd8dbc184
[LV] Move code to prepare VPlan for epilogue vector loop to helper (NFC)
Move code to prepare the VPlan for the epilogue vector loop to a helper
to reduce size and complexity of processLoop.
2024-12-09 21:56:10 +00:00
Kazu Hirata
9099d694f6 [Vectorize] Fix a warning
This patch fixes:

  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:2699:49: error:
  captured structured bindings are a C++20 extension
  [-Werror,-Wc++20-extensions]
2024-12-09 10:26:48 -08:00
Igor Kirillov
337936a83b
[LV] Ignore some costs when loop gets fully unrolled (#106699)
When VF has a fixed width and equals the number of iterations, and we are not
tail folding by masking, comparison instruction and induction operation will be DCEed later.
Ignoring the costs of these instructions improves the cost model.
2024-12-09 18:17:52 +00:00
Simon Pilgrim
54c6a592a0 [VectorCombine] Add explicit CostKind to all getMemoryOpCost calls. NFC.
We currently hardwire CostKind to TTI::TCK_RecipThroughput which matches the default CostKind for getMemoryOpCost.
2024-12-09 13:39:19 +00:00
Simon Pilgrim
b3e498799e [VectorCombine] Add explicit CostKind to all getCmpSelInstrCost calls. NFC.
We currently hardwire CostKind to TTI::TCK_RecipThroughput which matches the default CostKind for getCmpSelInstrCost.
2024-12-09 13:25:32 +00:00
Simon Pilgrim
37cb9bdeca [VectorCombine] Add explicit CostKind to all getArithmeticInstrCost calls. NFC.
We currently hardwire CostKind to TTI::TCK_RecipThroughput which matches the default CostKind for getArithmeticInstrCost.
2024-12-09 13:01:14 +00:00
Simon Pilgrim
9328cc0f67 [VectorCombine] Add explicit CostKind to all getShuffleCost calls. NFC.
We currently hardwire CostKind to TTI::TCK_RecipThroughput which matches the default CostKind for getShuffleCost.
2024-12-09 13:01:14 +00:00
Simon Pilgrim
7831c5e483
[VectorCombine] Pull out TargetCostKind argument to allow globally set cost kind value (#118652)
Don't use TCK_RecipThroughput independently in every VectorCombine fold.

Some prep work to allow a potential future patch to use VectorCombine to optimise for code size for -Os/Oz builds (setting TCK_CodeSize instead of TCK_RecipThroughput).

There's still more cleanup to do as a lot of get*Cost calls are relying on the default TargetCostKind value (usually TCK_RecipThroughput but not always).
2024-12-09 12:05:07 +00:00
Florian Hahn
eff0d8103c
[VPlan] Adjust original position of convertToConcreteRecipes.
Restore the original position of the call before afef545efab77a8
to fix a number of crashes.
2024-12-08 21:52:51 +00:00
Florian Hahn
afef545efa
[VPlan] Address post-commit for #114305.
Apply suggested renaming and adjust placement as suggested in
https://github.com/llvm/llvm-project/pull/114305. Also drop unneeded
RPOT creation.
2024-12-08 21:24:19 +00:00
Florian Hahn
ec22b1ab47
[VPlan] Iterate over blocks in VPlan::execute in RPOT (NFC).
This prepares for more complex CFGs in VPlan, as in
    https://github.com/llvm/llvm-project/pull/114292
    https://github.com/llvm/llvm-project/pull/112138
2024-12-07 10:19:27 +00:00
Florian Hahn
156da98683
[VPlan] Move printing final VPlan to ::execute (NFC).
This moves printing of the final VPlan to ::execute. This ensures the
final VPlan is printed, including recipes that get introduced by late,
lowering transforms and skeleton construction.

Split off from https://github.com/llvm/llvm-project/pull/114292, to
simplify the diff.
2024-12-07 09:39:10 +00:00
Alexey Bataev
376dad72ab [SLP]Move resulting vector before inert point, if the late generated buildvector fully matched
If the perfect diamond match was detected for the postponed buildvectors
and the vector for the previous node comes after the current node, need
to move the vector register before the current inserting point to
prevent compiler crash.

Fixes #119002
2024-12-06 13:54:48 -08:00
Florian Hahn
6797b0f0c0
[VPlan] Use RPOT for VPlan codegen and printing.
This split off changes for more complex CFGs in VPlan from both
    https://github.com/llvm/llvm-project/pull/114292
    https://github.com/llvm/llvm-project/pull/112138

This simplifies their respective diffs.
2024-12-06 21:49:00 +00:00
Florian Hahn
7f7f540a48
Reapply "[VPlan] Update scalar induction resume values in VPlan. (#110577)"
This reverts commit f09b16e2671cbcdf7cb7dc7ed705db092a9deda1.

The crash when building llvm-test-suite with stage2 should have been
fixed by 1091fad31a83d5ab87eb6fa11fe3bdb3f0d152ea.
2024-12-06 19:41:51 +00:00
Nikita Popov
f09b16e267 Revert "[VPlan] Update scalar induction resume values in VPlan. (#110577)"
This reverts commit 0678e2058364ec10b94560d27ec7138dfa003287.
This reverts commit 1091fad31a83d5ab87eb6fa11fe3bdb3f0d152ea.

Causes crashes in llvm-test-suite when using stage 2 clang.
2024-12-06 18:01:42 +01:00
Florian Hahn
1091fad31a
[VPlan] Fix stack-use-after-scope in VPInstruction::generate (NFC).
Fix stack-use-after-scope introduced in 0678e2058364ec by pulling out
the vector to a dedicated variable.

Should fix ASan/MSan failures, including
https://lab.llvm.org/buildbot/#/builders/169/builds/6111.
2024-12-06 16:50:54 +00:00
Florian Hahn
4f7f71b7bc
[VPlan] Compare APInt instead of getSExtValue to fix crash in unroll.
getSExtValue assumes the result fits in 64 bits, but this may not be the
case for indcutions with wider types. Instead, directly perform the
compare on the APInt for the ConstantInt.

Fixes https://github.com/llvm/llvm-project/issues/118850.
2024-12-06 16:28:49 +00:00
Nikita Popov
6307e4b31e Revert "[SLP] NFC. Replace TreeEntry::setOperandsInOrder with VLOperands. (#113880)"
This reverts commit 94fbe7e3ae7c0ce4e9a7d801e7700457a36f731d.

Causes a crash when linking mafft in ReleaseLTO-g config.
2024-12-06 14:27:03 +01:00
Anutosh Bhat
89e919fb0d
Fix warnings while compiling SLPVectorizer.cpp (#118051)
Towards #118048

I was building llvm (clang and lld) for webassembly and came across
these warnings. Not sure if they are seen in our builds too.
```
/Users/anutosh491/work/llvm-project/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp:6924:67: warning: comparison of integers of different signs: 'typename iterator_traits<user_iterator_impl<User>>::difference_type' (aka 'long') and 'unsigned int' [-Wsign-compare]
 6924 |               if (std::distance(LI->user_begin(), LI->user_end()) !=
      |                   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^
 6925 |                       LI->getNumUses())
      |                       ~~~~~~~~~~~~~~~~
[ 79%] Building CXX object lib/Transforms/Instrumentation/CMakeFiles/LLVMInstrumentation.dir/PGOInstrumentation.cpp.o
/Users/anutosh491/work/llvm-project/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp:9754:43: warning: comparison of integers of different signs: 'typename iterator_traits<Value *const *>::difference_type' (aka 'long') and 'unsigned int' [-Wsign-compare]
 9754 |               count(Slice, Slice.front()) ==
      |               ~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^
 9755 |                   (isa<UndefValue>(Slice.front()) ? VF - 1 : 1)) {
 ```


This PR tries to address those warnings.
2024-12-06 08:11:39 -05:00
Florian Hahn
0678e20583
[VPlan] Update scalar induction resume values in VPlan. (#110577)
Updated ILV.createInductionResumeValues (now createInductionResumeVPValue)
to directly update the VPIRInstructions wrapping the original phis with the 
created resume values.

This is the first step towards modeling them completely in VPlan.
Subsequent patches will move creation of the resume values completely
into VPlan.

Depends on https://github.com/llvm/llvm-project/pull/109975.

PR: https://github.com/llvm/llvm-project/pull/110577
2024-12-06 12:26:19 +00:00
Florian Hahn
f081ffe701
[LV] Simplify & clarify bypass handling for IV resume values (NFC)
Split off NFC part refactoring from
https://github.com/llvm/llvm-project/pull/110577. This simplifies and
clarifies induction resume value creation for bypass blocks.
2024-12-06 11:33:30 +00:00
vporpo
eeb55d3af6
[SandboxVec][DAG] Update MemDGNode chain upon instr creation (#116896)
The DAG maintains a chain of MemDGNodes that links together all the
nodes that may touch memroy.
Whenever a new instruction gets created we need to make sure that this
chain gets updated. If the new instruction touches memory then its
corresponding MemDGNode should be inserted into the chain.
2024-12-05 20:23:06 -08:00
Han-Kuan Chen
94fbe7e3ae
[SLP] NFC. Replace TreeEntry::setOperandsInOrder with VLOperands. (#113880)
To reduce repeated code, TreeEntry::setOperandsInOrder will be replaced
by VLOperands.
Arg_size will be provided to make sure other operands will not be
reorderd when VL[0] is IntrinsicInst (because APO is a boolean value).
In addition, BoUpSLP::reorderInputsAccordingToOpcode will also be
removed since it is simple.
2024-12-06 12:03:23 +08:00
Florian Hahn
a7fda0e1e4
[VPlan] Introduce VPScalarPHIRecipe, use for can & EVL IV codegen (NFC). (#114305)
Introduce a general recipe to generate a scalar phi. Lower
VPCanonicalIVPHIRecipe and VPEVLBasedIVRecipe to VPScalarIVPHIrecipe
before plan execution, avoiding the need for duplicated ::execute
implementations. There are other cases that could benefit, including
in-loop reduction phis and pointer induction phis.

Builds on a similar idea as
https://github.com/llvm/llvm-project/pull/82270.

PR: https://github.com/llvm/llvm-project/pull/114305
2024-12-03 14:53:51 +00:00
Ramkumar Ramachandra
2a0ee090db
IVDesc: strip redundant arg in getOpcode call (NFC) (#118476) 2024-12-03 13:40:51 +00:00
Han-Kuan Chen
f71ea4bc1b
[SLP][REVEC] reorderNodeWithReuses should not be called if all users of a TreeEntry are ShuffleVectorInst. (#118260) 2024-12-03 09:04:04 +08:00