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Author	SHA1	Message	Date
Youngsuk Kim	0f0a96b862	[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017 ) Remove the extraneous '+0' immediate offset part in PTX load/stores, to improve readability of output PTX code.	2024-10-19 10:05:36 -04:00
Durgadoss R	d5e9691509	[NVPTX] Add elect.sync Intrinsic (#104780 ) This patch adds an NVVM intrinsic and NVPTX codegen for the elect.sync PTX instruction. Lit tests are added in elect.ll and verified through ptxas. PTX ISA reference: https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-elect-sync Signed-off-by: Durgadoss R <durgadossr@nvidia.com>	2024-08-20 20:46:05 +05:30

Author

SHA1

Message

Date

Youngsuk Kim

0f0a96b862

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017 )

Remove the extraneous '+0' immediate offset part in PTX load/stores, to
improve readability of output PTX code.

2024-10-19 10:05:36 -04:00

Durgadoss R

d5e9691509

[NVPTX] Add elect.sync Intrinsic (#104780 )

This patch adds an NVVM intrinsic and NVPTX codegen for the elect.sync
PTX instruction. Lit tests are
added in elect.ll and verified through ptxas.

PTX ISA reference:

https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-elect-sync

Signed-off-by: Durgadoss R <durgadossr@nvidia.com>

2024-08-20 20:46:05 +05:30

2 Commits