This patch adds icmp+select patterns for integer min/max matchers in
SDPatternMatch, similar to those in IR PatternMatch.
Reapply #111774.
Closes#108218.
This PR is related to #99591. In this PR, instead of modifying how the
legalisation occurs depending on surrounding instructions, we refine
after legalisation.
This PR has two parts:
* `SDPatternMatch/MatchContext`: Modify a little bit the code to match
Operands (used by `m_Node(...)`) and Unary/Binary/Ternary Patterns to
make it compatible with `VPMatchContext`, instead of only `m_Opc`
supported. Some tests were added to ensure no regressions.
* `DAGCombiner`: Add a `foldSubCtlzNot` which detect and rewrite the
patterns using matching context.
Remaining Tasks:
- [ ] GlobalISel
- [ ] Currently the pattern matching will occur even before
legalisation. Should I restrict it to specific stages instead ?
- [ ] Style: Add a visitVP_SUB ?? Move `foldSubCtlzNot` in another
location for style consistency purpose ?
@topperc
---------
Co-authored-by: v01dxyz <v01dxyz@v01d.xyz>
Add support for matching with `SDNodeFlags` i.e `add` with `nuw`.
This patch adds helpers for `or disjoint` or `zext nneg` with the same
names as we have in IR/PatternMatch api.
Closes#103060
Currently, when using a VP match context with `sd_context_match`, only Opcode matching is possible (`m_Opc(Opcode)`).
This PR suggest a way to make patterns with Operands (eg `m_Node`, `m_Add`, ...) works with a VP context.
This PR blocks another PR https://github.com/llvm/llvm-project/pull/102877.
Co-authored-by: v01dxyz <v01dxyz@v01d.xyz>
This avoids another unserializable field. Move the DbgInfoAvailable
field into the AsmPrinter, which is only really a cache/convenience
bit for checking a direct IR module metadata check.
Context: https://github.com/llvm/llvm-project/pull/95365#discussion_r1638236603
The current implementation of `m_SExt` matches both `ISD::SIGN_EXTEND` and `ISD::SIGN_EXTEND_INREG`. However, in cases where we specifically need to match _only_ `ISD::SIGN_EXTEND`, such as in the SelectionDAG graph below, this can lead to issues and unintended combinations.
```
SelectionDAG has 13 nodes:
t0: ch,glue = EntryToken
t2: v2i32,ch = CopyFromReg t0, Register:v2i32 %0
t21: v2i32 = sign_extend_inreg t2, ValueType:ch:v2i8
t4: v2i32,ch = CopyFromReg t0, Register:v2i32 %1
t22: v2i32 = sign_extend_inreg t4, ValueType:ch:v2i8
t23: v2i32 = avgfloors t21, t22
t24: v2i32 = sign_extend_inreg t23, ValueType:ch:v2i8
t15: ch,glue = CopyToReg t0, Register:v2i32 $d0, t24
t16: ch = AArch64ISD::RET_GLUE t15, Register:v2i32 $d0, t15:1
```
Akin to `llvm::PatternMatch` and `llvm::MIPatternMatch`, the
`llvm::SDPatternMatch` introduced in this patch provides a DSL-alike
framework to match SDValue / SDNode with a more succinct syntax.
