516869 Commits

Author SHA1 Message Date
Min-Yih Hsu
ab5d3c9d35
[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009)
Split the scheduling classes of VMADC/VMSBC away from that of VADC/VSBC.
Because the former are technically mask-producing instructions rather
than normal vector arithmetics, which might have different performance
characteristics on some processors.

This is effectively NFC.
2024-10-28 09:37:54 -07:00
CarolineConcatto
106259510f
[AArch64]Add convert and multiply-add SIMD&FP assembly/disassembly in… (#113296)
…structions

This patch adds the following instructions:
Conversion between floating-point and integer:
  FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU}
  {S,U}CVTF
Advanced SIMD three-register extension:
  FMMLA

According to https://developer.arm.com/documentation/ddi0602

Co-authored-by: Marian Lukac marian.lukac@arm.com
Co-authored-by: Spencer Abson spencer.abson@arm.com
2024-10-28 16:36:02 +00:00
Petr Kurapov
7a710110fc
[MLIR][Vector] Remove unused and unimplemented Vector_WarpExecuteOnLa… (#112338)
…ne0Op builder

Removing the declaration instead of implementing the builder as
discussed in #110106
2024-10-28 17:12:12 +01:00
Boaz Brickner
80f38fbdcf
[clang] [NFC] Deduplicate the logic between StringMapEntry.first() and StringMapEntry.getKey() (#113735) 2024-10-28 09:10:07 -07:00
Aiden Grossman
eb53d08bce
[llvm-exegesis] Add Pfm Counters for SapphireRapids (#113847)
This patch adds the appropriate hookups in X86PfmCounters.td for
SapphireRapids. This is mostly to fix errors when some of my jobs that
only really need dummy counters get scheduled on sapphire rapids
machines, but figured I might as well do it properly while here. I do
not have hardware access to test this currently, but this matches
exactly with what is in the libpfm source code.
2024-10-28 09:07:14 -07:00
Craig Topper
5ac3f3c45c
[RISCV] Add DestEEW = EEW1 to VMADC. (#113013)
It was present on VMSBC but not VMADC. Reorder the instructions to avoid
duplicate 'let' statements.
2024-10-28 09:06:12 -07:00
Simon Pilgrim
670512b5c3 [AArch64] Regenerate srem-lkk.ll to add missing asm comments
Reduces diff in #112588
2024-10-28 16:00:45 +00:00
Brox Chen
b27acebe63
[AMDGPU][True16][test] update VOPC/VOPCX test for true16/fake16 (#112829)
This is a non-functional change

update GFX11/GFX12 VOPC/VOPCX asm/dasm test for true16/fake16:

1. duplicate files to be true16/fake16 by adding
"-mattr=+real-true16/-mattr=-real-true16" while true16 test file will be
updated to true16 format when the true16 instructions are supported
2. sort "*t16_err.s" and "*t16_promote.s" tests to alphabetic order.
tests to alphabetic order. This is for the upcoming true16 mc changes,
and mainly trying to help repo maintainer to resolve conflicts in the
tests quickly. A script is proposed to help for the sorting
https://github.com/llvm/llvm-project/pull/111769. Since these two files
are t16 only, it should not create conflicts in downstream branches
3. add `-filetype=null` to seperate stdout and stderr to avoid
disordered output from llvm-mc
2024-10-28 11:57:00 -04:00
Momchil Velikov
53f7f8ecca
[Clang][AArch64] Fix Pure Scalables Types argument passing and return (#112747)
Pure Scalable Types are defined in AAPCS64 here:

https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#pure-scalable-types-psts

And should be passed according to Rule C.7 here:

https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#682parameter-passing-rules

This part of the ABI is completely unimplemented in Clang, instead it
treats PSTs sometimes as HFAs/HVAs, sometime as general composite types.

This patch implements the rules for passing PSTs by employing the
`CoerceAndExpand` method and extending it to:
* allow array types in the `coerceToType`; Now only `[N x i8]` are
considered padding.
* allow mismatch between the elements of the `coerceToType` and the
elements of the `unpaddedCoerceToType`; AArch64 uses this to map
fixed-length vector types to SVE vector types.

Corectly passing a PST argument needs a decision in Clang about whether
to pass it in memory or registers or, equivalently, whether to use the
`Indirect` or `Expand/CoerceAndExpand` method. It was considered
relatively harder (or not practically possible) to make that decision in
the AArch64 backend.
Hence this patch implements the register counting from AAPCS64 (cf.
`NSRN`, `NPRN`) to guide the Clang's decision.
2024-10-28 15:43:14 +00:00
Abhina Sree
7d1e98c7d3
[AIX][SystemZ][z/OS] Disable test for AIX, z/OS due to missing DWARF sections (#113910)
This patch disables the testcase for AIX and z/OS due to incomplete
DWARF support.
2024-10-28 11:34:57 -04:00
Nikolas Klauser
3ac75ee8ec
Revert "[runtimes] Allow building against an installed LLVM tree" (#113920)
Reverts llvm/llvm-project#86209

This patch breaks running tests locally, which is extremely disruptive
to libc++ development.
2024-10-28 16:25:58 +01:00
Sushant Gokhale
c9f01f699c
[SLP][AArch64][NFC] Add more tests for SLP vectorization of div (#113876)
Currently, we dont have much tests that show SLP outcome for integer
divisions. This patch adds tests for same.

In certain scenarios, for Neon, vectorization is profitable. An attempt
would be made in future to improve the cost-model for the same.
2024-10-28 20:37:41 +05:30
Luke Lau
40363d506d [RISCV] Add cost model tests for fp rounding ops for bf16. NFC 2024-10-28 14:59:06 +00:00
Vlad Serebrennikov
d83485a080
[clang][NFC] Add test for CWG issues about linkage in cross-TU context (#113736)
[CWG279](https://cplusplus.github.io/CWG/issues/279.html) Correspondence
of "names for linkage purposes"
====================

[P1787R6](https://wg21.link/p1787r6):
> CWG1884, CWG279, and CWG338 are resolved by defining entity identity
explicitly.

In both cases discussed in the issue, declaration matching succeeds per
[[basic.link]/8](https://eel.is/c++draft/basic.link#8), thanks to the
> considering declarations of unnamed types to introduce their names for
linkage purposes, if any ([dcl.typedef], [dcl.enum])

and

> they both declare names with external linkage

parts. Which means that both pairs of declarations of `S` and `S2`
declare the same entity.
[[basic.link]/11](https://eel.is/c++draft/basic.link#11) is also
satisfied, because in all cases type is declared.

Then cases diverge. `S` is a pair of a forward declaration and a
definition, which means it's not a subject to
[[basic.def.odr]/15](https://eel.is/c++draft/basic.def.odr#15), hence
it's well-formed. Whereas `S2` is a pair of two definitions, so they are
subjects to
[[basic.def.odr]/15](https://eel.is/c++draft/basic.def.odr#15), which
they do not satisfy due to the violation of the following requirement:

> — Each such definition shall consist of the same sequence of tokens,
<...>

Because per [[class.pre/2]](https://eel.is/c++draft/class#pre-2), class
definition is class-specifier, which includes class-head, but class-head
is different between definitions.



[CWG338](https://cplusplus.github.io/CWG/issues/338.html) Enumerator
name with linkage used as class name in other translation unit
====================

[P1787R6](https://wg21.link/p1787r6):
> CWG1884, CWG279, and CWG338 are resolved by defining entity identity
explicitly.

I believe this CWG issue points to the same underlying issue with old
[basic.link]/9 as CWG1884 (see below), so I'm calling it a duplicate of
CWG1884. Cases described there are a part of an extensive CWG1884 test.
Also worth noting that enumerators don't have linkage these days.



[CWG1884](https://cplusplus.github.io/CWG/issues/1898.html) Unclear
requirements for same-named external-linkage entities
====================

[P1787R6](https://wg21.link/p1787r6):
> CWG1884, CWG279, and CWG338 are resolved by defining entity identity
explicitly.

[basic.link]/9 quoted in the issue is now split into several pieces.

> Two names that are the same (6.1 [basic.pre])

I believe this is corresponding declarations now, defined in
[[basic.scope.scope]/4](https://eel.is/c++draft/basic.scope#scope-4).

> and that are declared in different scopes shall denote the same
variable, function, type, enumerator, template or namespace if

This is covered by
[[basic.link]/11](https://eel.is/c++draft/basic.link#11) after it's
determined by [[basic.link]/8](https://eel.is/c++draft/basic.link#8)
that two declarations declare the same entity.

> — both names have external linkage or else both names have internal
linkage and are declared in the same translation unit; and
> — both names refer to members of the same namespace or to members, not
by inheritance, of the same class; and

Most of this is covered by
[[basic.link]/8](https://eel.is/c++draft/basic.link#8).

> — when both names denote functions, the parameter-type-lists of the
functions (9.3.4.6 [dcl.fct]) are identical; and
> — when both names denote function templates, the signatures (13.7.7.2
[temp.over.link]) are the same.

This is corresponding overloads now, defined in
[[basic.scope.scope]/4](https://eel.is/c++draft/basic.scope#scope-4).

> Among other things, it should be clarified that "declared in" refers
to the namespace of which the name is a member, not the lexical scope in
which the declaration appears (which affects friend declarations,
block-scope extern declarations, and elaborated-type-specifiers).

This is addressed by "have the same target scope" part of
[[basic.link]/8](https://eel.is/c++draft/basic.link#8).

The tests basically test
[[basic.link]/11](https://eel.is/c++draft/basic.link#11) from the
following standpoint:
> The intent is that this rule prevents declaring a name with extenal
linkage to be, for instance, a type in one translation unit and a
namespace in a different translation unit.

See the comment in the beginning of the test for details on testing
approach. Reviewers are advised to check compiler output for any
surprises, but if they are in a hurry, they can search for `FIXME`,
`OK`, and `#cwg1884` to see the most of irregularities in Clang behavior
across the test (not all of them are incorrect behavior, though).
2024-10-28 18:48:23 +04:00
Jan Voung
1f6741c164
[clang][dataflow] Don't clear cached field state if field is const (#113698)
... in the unchecked optional access model.
2024-10-28 10:28:02 -04:00
Yusuke MINATO
bd6ab32e6e
Revert "[flang] Integrate the option -flang-experimental-integer-overflow into -fno-wrapv" (#113901)
Reverts llvm/llvm-project#110063 due to the performance regression on
503.bwaves_r in SPEC2017.
2024-10-28 14:19:20 +00:00
Joseph Huber
42eb54b774
[Clang] Put offloading globals in the .llvm.rodata.offloading section (#111890)
Summary:
For our offloading entries, we currently store all the string names of
kernels that the runtime will need to load from the target executable.
These are available via pointer in the `__tgt_offload_entry` struct,
however this makes it difficult to obtain from the object itself. This
patch simply puts the strings in a named section so they can be easily
queried.

The motivation behind this is that when the linker wrapper is doing
linking, it wants to know which kernels the host executable is calling.
We *could* get this already via the `.relaomp_offloading_entires`
section and trawling through the string table, but that's quite annoying
and not portable. The follow-up to this should be to make the linker
wrapper get a list of all used symbols the device link job should count
as "needed" so we can handle static linking more directly.
2024-10-28 07:17:50 -07:00
Joseph Huber
d4c4180417
[Clang] Add a flag to include GPU startup files (#112025)
Summary:
The C library for GPUs provides the ability to target regular C/C++
programs by providing the C library and a file containing kernels that
call the `main` function. This is mostly used for unit tests, this patch
provides a quick way to add them without needing to know the paths. I
currently do this explicitly, but according to the libc++ contributors
we don't want to need to specify these paths manually. See the
discussion in https://github.com/llvm/llvm-project/pull/104515.

I just default to `lib/` if the target-specific one isn't found because
the linker will handle giving a reasonable error message if it's not
found. Basically the use-case looks like this.

```console
$ clang test.c --target=amdgcn-amd-amdhsa -mcpu=native -startfiles -stdlib
$ amdhsa-loader a.out
PASS!
```
2024-10-28 07:17:19 -07:00
Alexey Bataev
7152bf3bc8 [SLP]Do not create new vector node if scalars fully overlap with the existing one
If the list of scalars vectorized as the part of the same vector node,
no need to generate vector node again, it will be handled as part of
overlapping matching.

Fixes #113810
2024-10-28 06:59:41 -07:00
SpencerAbson
ce0368eb84
[AArch64] Add assembly/disassembly for PMLAL/PMULL instructions (#113564)
This patch adds assembly/disassembly for the following SVE_AES2
instructions

    -  PMLAL
    -  PMULL
- In accordance with:
https://developer.arm.com/documentation/ddi0602/latest/
2024-10-28 13:55:16 +00:00
Guillaume Chatelet
b1ede8fcb4
[reland][libc][bazel] Enable software prefetching for memcpy (#113886)
This will affect only Bazel configuration for now.
This is a reland of #108939 which has been reverted because of codegen
issues fixed by https://github.com/llvm/llvm-project/pull/113161.
2024-10-28 14:43:10 +01:00
Haojian Wu
9090430d41
Add clang::lifetimebound annotation to StringRef constructors. (#113878)
Adding the lifetimebound annotation to the ArrayRef's array constructor
can enable us to detect the following use-after-free issues:

```
llvm::StringRef TestZoneName() {
   char test[] = "foo"; // oops, missing static
   return test; // use-after-free.
}
```

See #113533
2024-10-28 14:28:07 +01:00
Benjamin Maxwell
ddd463be7e
[AArch64] Add getStreamingHazardSize() to AArch64Subtarget (#113679)
This is defined by the `-aarch64-streaming-hazard-size` option or its
alias `-aarch64-stack-hazard-size` (the original name). It has been
renamed to be more general as this option will (for the time being) be
used to detect if the current target has streaming mode memory hazards.

---------

Co-authored-by: Hari Limaye <hari.limaye@arm.com>
2024-10-28 13:01:22 +00:00
Alex Bradbury
ba7555e640
[RISCV] Mark the RVA23S64 and RVA23U64 profiles as non-experimental (#113826)
All of the extensions used by these profile are themselves
non-experimental, and RVA23 was just ratified

<https://riscv.org/announcements/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/>.

<https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc>

We lack a way of expressing `Ss1p13` (supervisor architecture 1.13), but
this is a problem we have for RVA22 (Ss1p12) and RVA20 (Ss1p11) so I
don't feel it's a blocker.
2024-10-28 12:56:47 +00:00
LLVM GN Syncbot
1164bd7747 [gn build] Port e146c1867e8d 2024-10-28 11:56:44 +00:00
LLVM GN Syncbot
2a4bab3fac [gn build] Port cfde4fbccf5d 2024-10-28 11:56:43 +00:00
LLVM GN Syncbot
595ec4e4be [gn build] Port 5aa1275d03b6 2024-10-28 11:56:42 +00:00
LLVM GN Syncbot
cbaecb5d29 [gn build] Port 3d6923dbac16 2024-10-28 11:56:42 +00:00
LLVM GN Syncbot
233e64d8e4 [gn build] Port 0be1883c36fc 2024-10-28 11:56:40 +00:00
dong-miao
75c75fc16e
[RISCV]Add svvptc extension (#113882) 2024-10-28 22:54:51 +11:00
Simon Pilgrim
056cf936a7
[DAG] Fold (and X, (bswap/bitreverse (not Y))) -> (and X, (not (bswap/bitreverse Y))) (#112547)
On ANDNOT capable targets we can always do this profitably, without ANDNOT we only attempt this if we don't introduce an additional NOT

Fixes #112425
2024-10-28 11:52:44 +00:00
Simon Pilgrim
d6d4569dd9 Fix MSVC "signed/unsigned mismatch" warnings. NFC. 2024-10-28 11:45:36 +00:00
Luke Lau
0cbccb13d6
[RISCV] Remove support for pre-RA vsetvli insertion (#110796)
Now that LLVM 19.1.0 has been out for a while with post-vector-RA
vsetvli insertion enabled by default, this proposes to remove the flag
that restores the old pre-RA behaviour so we only have one configuration
going forward.

That flag was mainly meant as a fallback in case users ran into issues,
but I haven't seen anything reported so far.
2024-10-28 11:31:18 +00:00
Momchil Velikov
1df5c94343
[AArch64] Implement FP8 floating-point mode helper intrinsics (#100608)
Implement FP8 mode helper intrinsics (as inline functions) as
specified in ACLE 2024Q3 "14.2 Helper intrinsics"

https://github.com/ARM-software/acle/releases/download/r2024Q3/acle-2024Q3.pdf
2024-10-28 11:22:38 +00:00
Discookie
f5ff3a560f
[clang-tidy] Do not emit file path for anonymous enums in readability-enum-initial-value check (#112496)
Previously the name of anonymous enums in the check were `enum 'enum
(unnamed at /full/path/to/file.c:1:1)'`, which breaks reproducibility of
clang-tidy reports when the analyzed project is in a different folder.
2024-10-28 11:19:22 +00:00
SpencerAbson
64148944c5
[AArch64] Add assembly/disassembly for zeroing SVE2 integer instructions (#113473)
This patch adds assembly/disassembly for the following SVE2.2
instructions

    -  SQABS  (zeroing)
    -  SQNEG  (zeroing)
    -  URECPE (zeroing)
    -  USQRTE (zeroing)

- Refactor the existing merging forms to remove the now redundant bit 17
argument.
- In accordance with:
https://developer.arm.com/documentation/ddi0602/latest/
2024-10-28 10:41:07 +00:00
Jonas Paulsson
09160a9821
[SystemZ] Silence compiler warning (#113894)
Use SystemZ::NoRegister instead of 0 in
SystemZTargetLowering::getRegisterByName().
2024-10-28 11:32:39 +01:00
Brandon Wu
f5d8a485e2
[RISCV] Fix typo in UserGuides.rst. NFC (#113861) 2024-10-28 18:30:21 +08:00
Jie Fu
e6fcf349ef [clang-tidy] Remove unused variable (NFC)
/llvm-project/clang-tools-extra/clang-tidy/bugprone/NondeterministicPointerIterationOrderCheck.cpp:60:29:
error: unused variable 'AlgoName' [-Werror,-Wunused-variable]
      const llvm::StringRef AlgoName = ClassTemplate->getName();
                            ^
1 error generated.
2024-10-28 18:28:52 +08:00
Adrian Vogelsgesang
09c258ef6a
[NFC][lldb-dap] Clean-up includes (#113839)
This commit cleans up the includes in the `lldb-dap` subfolder. The main
motivation was that I got annoyed by `clangd` always complaining about
unused includes while working on lldb-dap.
2024-10-28 11:01:57 +01:00
Yingwei Zheng
f78610af3f
[InstCombine] Add function attribute instcombine-no-verify-fixpoint (#113822)
This patch introduces a function attribute
`instcombine-no-verify-fixpoint` to avoids disabling fix-point
verification for unrelated tests in the same file.
Address comment
https://github.com/llvm/llvm-project/pull/112642#discussion_r1804714387.
2024-10-28 17:45:08 +08:00
Mirko Brkušanin
fa4790e404
[AMDGPU][MC] Fix disassembler for VIMAGE when non-first vaddr is v0 (#113569)
For disassembler tables we use *V1_V4* variants for VIMAGE and then
remove unused vaddr fields. *V1_V1* variant, which has every vaddr
field other than vaddr0 set to 0, was also enabled and caused confusion
when decoding cases which used v0 (whose encoded value is 0)
2024-10-28 10:43:18 +01:00
Luke Lau
96f5c68350
[RISCV] Lower @llvm.experimental.vector.compress for zvfhmin/zvfbfmin (#113770)
This is a follow up to #113291 and handles f16/bf16 with zvfhmin and
zvfbmin.
2024-10-28 09:37:06 +00:00
Alex Bradbury
43a5719d9f
[RISCV] Use Sha extension in RVA23S64 profile (#113823)
In the ratified version of the RVA23S64 definition, the Sha extension is
now used to group together the set of hypervisor related extensions.

<https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc>
2024-10-28 09:22:09 +00:00
Jack Styles
933a56674e
[PAuthLR] Add Missing Break Statement for MachineOperand Switch Statement (#113883)
There was a missing break, which led to an unannotated fallthrough when
merging #112171. This has caused sanitizer builds to fail.

This adds the missing break in the switch statement to ensure that the
fallthrough does not occur.
2024-10-28 09:08:48 +00:00
Oliver Stannard
dff114b356
[ARM] Optimise non-ABI frame pointers (#110286)
With -fomit-frame-pointer, even if we set up a frame pointer for other
reasons (e.g. variable-sized or over-aligned stack allocations), we
don't need to create an ABI-compliant frame record. This means that we
can save all of the general-purpose registers in one push, instead of
splitting it to ensure that the frame pointer and link register are
adjacent on the stack, saving two instructions per function.
2024-10-28 09:01:06 +00:00
Vassil Vassilev
f6b513a785 Revert "Add explicit symbol visibility macros to InstrProfData.inc (#110732)"
This reverts commit d7ca703eab7997814de425eaa4fd888563d78831 in llvm/llvm-project#110732
2024-10-28 08:57:57 +00:00
vabridgers
3d6923dbac
RFC: [clang-tidy] [analyzer] Move nondeterministic pointer usage check to tidy (#110471)
This change moves the `alpha.nondeterministic.PointerSorting` and
`alpha.nondeterministic.PointerIteration` static analyzer checkers to a
single `clang-tidy` check. Those checkers were implemented as simple
`clang-tidy` check-like code, wrapped in the static analyzer framework.
The documentation was updated to describe what the checks can and cannot
do, and testing was completed on a broad set of open-source projects.

Co-authored-by: Vince Bridgers <vince.a.bridgers@ericsson.com>
2024-10-28 03:53:36 -05:00
Thomas Fransham
14171b0b13
[Remarks] Fix missing include in HotnessThresholdParser for Expected (#113755)
The use of Expected<> requires llvm/Support/Error.h to be included.
2024-10-28 10:52:22 +02:00
Thomas Fransham
d7ca703eab
Add explicit symbol visibility macros to InstrProfData.inc (#110732)
Add explicit symbol visibility macros to InstrProfData.inc

Annotating these symbols will fix missing symbols for InstrProfTest when
using shared library builds on windows with explicit visibility macros
enabled.
Add a empty fallback definition for LLVM_ABI macro so the code works in
compiler-rt.

This is part of the work to enable LLVM_BUILD_LLVM_DYLIB and plugins on
window.

```
llvm\lld-link : error : undefined symbol: public: void ValueProfData::deserializeTo(InstrProfRecord&,  InstrProfSymtab*)
>>> referenced by unittests\ProfileData\InstrProfTest.cpp:1372 void ValueProfileReadWriteTest_value_prof_data_read_write_Test::TestBody()
```
2024-10-28 10:47:40 +02:00