516869 Commits

Author SHA1 Message Date
Asher Mancinelli
6af275b72e
[mlir][doc] Fix nitpicks in documentation (#114157)
A couple of these are probably up to preference, but the
grammar/capitalization changes are probably more critical for
readability.
2024-10-30 07:07:49 -07:00
c8ef
68daf7d27e
[Tooling/Inclusion] Add binary search related std::ranges symbols to the mapping. (#113796)
Fixes #94459.

This patch adds binary search related `std::ranges` symbols to the mapping.
2024-10-30 22:04:14 +08:00
Rahul Joshi
e6e04633c6
[NFC] Delete unused clang-formatted-file.txt/ClangFormattedStatus.rst files (#109220)
Looks like these files are generated by the
`generate_formatted_state.py` script as a "status report" of state of
clang-format compliance of files in the LLVM git repo. As such, they do
not belong to the repo itself, so deleting them.

Please see:
https://discourse.llvm.org/t/clang-docs-tools-clang-formatted-files-txt/82803
2024-10-30 07:02:07 -07:00
Nathan Gauër
cba70550cc
[SPIR-V] Fix BB ordering & register lifetime (#111026)
The "topological" sorting was behaving incorrectly in some cases: 
the exit of a loop could have a lower rank than a node in the loop.
This causes issues when structurizing some patterns, and also codegen
issues as we could generate BBs in the incorrect order in regard to the
SPIR-V spec.

Fixing this ordering alone broke other parts of the structurizer, which
by luck worked. Had to fix those.

Added more test cases, especially to test basic patterns.

I also needed to tweak/disable some tests for 2 reasons:
 - SPIR-V now required reg2mem/mem2reg to run. Meaning dead stores
   are optimized away. Some tests require tweaks to avoid having the
   whole function removed.
 - Mem2Reg will generate variable & load/stores. This generates
   G_BITCAST in several cases. And there is currently something wrong
   we do with G_BITCAST which causes MIR verifier to complain.
   Until this is resolved, I disabled -verify-machineinstrs flag on
   those tests.

---------

Signed-off-by: Nathan Gauër <brioche@google.com>
2024-10-30 14:57:32 +01:00
vdonaldson
8d406d882d
[flang] IEEE_REAL (#113948)
IEEE_REAL converts an integer or real argument to a real of a given
kind.
2024-10-30 09:56:42 -04:00
David Sherwood
7f498a865f
[CostModel][LoopVectorize] Move some loop vectoriser tests (#113702)
Many tests that were in test/Analysis/CostModel were actually
loop vectoriser tests. I've moved them as follows:

Analysis/CostModel/X86 -> Transforms/LoopVectorize/X86/CostModel
Analysis/CostModel/AArch64/arith-fp-frem.ll ->
  Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll
2024-10-30 13:50:02 +00:00
Simon Pilgrim
80c8ecd565 [VectorCombine] Add baseline "shuffle (binop (shuffle, shuffle)), undef" tests for #114101 2024-10-30 13:42:58 +00:00
Krzysztof Parzyszek
c478aab684
[flang][OpenMP] Parser support for DEPOBJ plus DEPEND, DESTROY, UPDATE (#114074)
Parse the DEPOBJ construct and the associated clauses, perform basic
semantic checks.
2024-10-30 08:36:08 -05:00
Nikolas Klauser
508263824f
[Clang] Start moving X86Builtins.def to X86Builtins.td (#106005)
This starts moving `X86Builtins.def` to be a tablegen file. It's quite
large, so I think it'd be good to move things in multiple steps to avoid
a bunch of merge conflicts due to the amount of time this takes to
complete.
2024-10-30 14:23:35 +01:00
Sander de Smalen
602f43686c
[AArch64] Add patterns for constructive splice. (#113912)
SVE2 adds the constructive splice instruction, which takes a tuple.
Even though the register allocator must ensure that the tuple uses
consecutive registers for the tuple, it's likely to be more efficient
than using the destructive splice instruction when the first operand
is reused.
2024-10-30 13:17:31 +00:00
Petar Avramovic
84b7bcfcac
GlobalISel/MachineIRBuilder: Construct DstOp with VRegAttrs (#113581)
Allow construction of DstOp with VRegAttrs.
Also allow construction with register class or bank and LLT.
Intended to be used in lowering code for reg-bank-select where
new registers need to have both register bank and LLT.
Add support for new type of DstOp in CSEMIRBuilder.
2024-10-30 14:15:42 +01:00
Brox Chen
6f973fd4ab
[AMDGPU][test] fix the error case in update_mc_test_check script (#112731)
update_mc_test_check script handle the "error case testline" wrong in
three cases:

1. when user select "--llvm-mc-binary" with a path, the script does not
add "not" on top of the "--llvm-mc-binary" and thus getting non-zero
exit code and failed.
2. When "not" is presented in runline while not all testlines are
expected to fail, the script need to check if the "not" is needed when
it execute llvm-mc line by line. Otherwise the script will fail on
testline which is passing.
3. When there are multiple runlines, the error checkline need to use
correct line offset for "[[LINE-X]]"

This patch solve these three issues
2024-10-30 09:02:40 -04:00
Jonas Hahnfeld
c4e135ec04
[ORC] Fix transfer to unknown ResourceTrackers (#114063)
When transferring resources, the destination tracker key may not be in
the internal map, invalidating iterators and value references. The added
test creates such situation and would fail before with "Finalized
allocation was not deallocated."

For good measure, fix the same pattern in RTDyldObjectLinkingLayer
which is harder to test because it "only" results in memory managers
being deleted in the wrong order.
2024-10-30 13:56:27 +01:00
Matthias Springer
217700baf7
[mlir][bufferization] Support bufferization of external functions (#113999)
This commit adds support for bufferizing external functions that have no
body. Such functions were previously rejected by One-Shot Bufferize if
they returned a tensor value.

This commit is in preparation of removing the deprecated
`func-bufferize` pass. That pass can bufferize external functions.

Also update a few comments.
2024-10-30 21:49:10 +09:00
Matthias Springer
ea050ab1a9
[mlir][Transforms][NFC] Dialect conversion: Reformat materialization error message (#114176)
This commit changes the format of the materialization error message.

Previously: `failed to legalize unresolved materialization from ('f64')
to 'f32' that remained live after conversion`
Now: `failed to legalize unresolved materialization from ('f64') to
('f32') that remained live after conversion`

This commit is in preparation of merging the 1:1 and 1:N dialect
conversions. At that point, target materializations may create more than
one SSA value. I am sending this change as a separate PR to keep the
main PR smaller.
2024-10-30 21:36:39 +09:00
Lukacma
15f63ec19c
[AARCH64] Add assembly/disassmbly for FIRST,LASTP instr. (#114049)
This patch adds assembly/disassembly and tests for new FIRSTP
and LASTP instructions introduced in
https://developer.arm.com/documentation/ddi0602/2024-09

---------

Co-authored-by: SpencerAbson <Spencer.Abson@arm.com>
2024-10-30 12:32:32 +00:00
SpencerAbson
85f3d5ca49
[AArch64] Add assembly/disassembly for SVE COMPACT (b/h) and EXPAND (#114053)
This patch adds assembly/disassembly support for the following SVE2.2
instructions

      - COMPACT (byte, halfword)
      - EXPAND

- Allow selection of `COMPACT` (word/halfword) in streaming mode if the
target has FEAT_SME2p2 (see [COMPACT ](
https://developer.arm.com/documentation/ddi0602/2024-09/SVE-Instructions/COMPACT--Copy-active-vector-elements-to-lower-numbered-elements-))
- Rename predicates guarding instructions that are illegal in streaming
SVE mode without FEAT_SME2p2
- In accordance with
https://developer.arm.com/documentation/ddi0602/2024-09/SVE-Instructions
Co-authored-by: Marian Lukac marian.lukac@arm.com
2024-10-30 12:11:34 +00:00
Sergio Afonso
55e4e3ff65
[Flang][OpenMP] Access full list of entry block syms and vars (NFC) (#113681)
This patch adds methods to `EntryBlockArgs` to access the full list of
entry block argument-related symbols and variables, in their standard
order. This helps centralizing this logic in as few places as possible
to avoid future inconsistencies.
2024-10-30 12:07:47 +00:00
Jay Foad
cea9dd833c
[CodeGen] Change MachineInstr::isConstantValuePHI to return Register. NFC. (#112901) 2024-10-30 11:58:59 +00:00
Simon Pilgrim
bc999ee57a [PhaseOrdering][X86] Add test coverage for #94546 2024-10-30 11:55:04 +00:00
Alexandros Lamprineas
5dac2db5a8
[FMV][AArch64] Remove features which can be expressed as a combination of others. (#113580)
Removes sve-bf16, sve-ebf16, and sve-i8mm since they are obsolete. One
could write target_version("sve+bf16") instead of sve-bf16 for instance.

Approved in ACLE as https://github.com/ARM-software/acle/pull/353
2024-10-30 11:53:50 +00:00
Enna1
fcfd64304f
[lld][ELF] Fix typo in help text for plugin-opt=opt-remarks-with-hotness (NFC) (#114016) 2024-10-30 19:25:08 +08:00
Simon Pilgrim
2de1fc8286 [PhaseOrdering][X86] Add additional test coverage for #49736
I've kept the old PR50392 tag since this is such an old issue....
2024-10-30 11:10:48 +00:00
Kiran Chandramohan
092a819e94
[Flang][OpenMP] Add frontend support for directives involving master (#113893)
Issue deprecation warning for these directives.
Lowering currently supports parallel master, for all other combined or
composite directives involving master, issue TODO errors.

Note: The first commit changes the formatting and generalizes the
deprecation message emission for reuse in the second commit. I can pull
it out into a separate commit if required.
2024-10-30 10:58:26 +00:00
Alex Rønne Petersen
f447cf15b2
[CSKY] Fix some typos in CPU feature descriptions (NFC) (#105774)
In Zig, we have a tool that updates our CPU model/feature data from
LLVM's. Noticed these typos when running it for LLVM 19.

Note: I don't have commit access.
2024-10-30 06:55:57 -04:00
Nikolas Klauser
0fb76bae6b
Reapply "[libc++] Simplify the implementation of std::sort a bit (#104902)" (#114023)
This reverts commit ef44e4659878f2. The patch was originally reverted
because it was
deemed to introduce a performance regression for small inputs, however
it also fixed
a previous performance regression for larger inputs. So overall, this
patch is desirable.
2024-10-30 11:51:55 +01:00
Simon Pilgrim
f7b5f0c805 [DAG] Fold (and X, (rot (not Y), Z)) -> (and X, (not (rot Y, Z)))
On ANDNOT capable targets we can always do this profitably, without ANDNOT we only attempt this if we don't introduce an additional NOT

Followup to #112547
2024-10-30 10:46:12 +00:00
Simon Pilgrim
03948882d3 Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFC
NumBits should be less than 20 so using an unsigned instead of size_t should be OK
2024-10-30 10:12:57 +00:00
Abid Qadeer
652988b658
[flang][debug] Support TupleType. (#113917)
Handling is similar to RecordType with following differences:

1. No check for cyclic references
2. No extra processing for lower bounds of array members.
3. No line information as TupleType is a lowering artefact and does not
really represent an entity in the code.
2024-10-30 09:52:56 +00:00
Mirko Brkušanin
e8b95a02bf
[AMDGPU][MC][NFC] Add more VIMAGE encoding tests (#114054)
These are primarily meant to test disassembler and that no more than
one variant per instruction is in DisassemblerTables as that can cause
confusion when decoding v0 (vgpr0) whose value when encoded is 0.
2024-10-30 10:45:33 +01:00
Chuanqi Xu
259eaa6878
[C++20] [Modules] Fix the duplicated static initializer problem (#114193)
Reproducer:

```
//--- a.cppm
export module a;
int func();
static int a = func();

//--- a.cpp
import a;
```

The `func()` should only execute once. However, before this patch we
will somehow import `static int a` from a.cppm incorrectly and
initialize that again.

This is super bad and can introduce serious runtime behaviors.

And also surprisingly, it looks like the root cause of the problem is
simply some oversight choosing APIs.
2024-10-30 17:27:04 +08:00
Mahesh-Attarde
e61a7dc256
[X86][AVX512] Use comx for compare (#113567)
We added AVX10.2 COMEF ISA in LLVM, This does not optimize correctly in
scenario mentioned below.
Summary
Input 
```
define i1 @oeq(float %x, float %y) {
    %1 = fcmp oeq float %x, %y
    ret i1 %1
}define i1 @une(float %x, float %y) {
    %1 = fcmp une float %x, %y
    ret i1 %1
}define i1 @ogt(float %x, float %y) {
    %1 = fcmp ogt float %x, %y
    ret i1 %1
}
// Prior AVX10.2, default code generation

oeq:                                    # @oeq
        cmpeqss xmm0, xmm1
        movd    eax, xmm0
        and     eax, 1
        ret
une:                                    # @une
        cmpneqss        xmm0, xmm1
        movd    eax, xmm0
        and     eax, 1
        ret
ogt:                                    # @ogt
        ucomiss xmm0, xmm1
        seta    al
        ret 
```

This patch will remove `cmpeqss` and `cmpneqss`. For complete transform
check unit test.

Continuing on what PR https://github.com/llvm/llvm-project/pull/113098
added

Earlier Legalization and combine expanded `setcc oeq:ch` node into `and`
and `setcc eq` , `setcc o`. From suggestions in community
new internal transform
```
Optimized type-legalized selection DAG: %bb.0 'hoeq:'
SelectionDAG has 11 nodes:
  t0: ch,glue = EntryToken
      t2: f16,ch = CopyFromReg t0, Register:f16 %0
      t4: f16,ch = CopyFromReg t0, Register:f16 %1
    t14: i8 = setcc t2, t4, setoeq:ch
  t10: ch,glue = CopyToReg t0, Register:i8 $al, t14
  t11: ch = X86ISD::RET_GLUE t10, TargetConstant:i32<0>, Register:i8 $al, t10:1

Optimized legalized selection DAG: %bb.0 'hoeq:'
SelectionDAG has 12 nodes:
  t0: ch,glue = EntryToken
        t2: f16,ch = CopyFromReg t0, Register:f16 %0
        t4: f16,ch = CopyFromReg t0, Register:f16 %1
      t15: i32 = X86ISD::UCOMX t2, t4
    t17: i8 = X86ISD::SETCC TargetConstant:i8<4>, t15
  t10: ch,glue = CopyToReg t0, Register:i8 $al, t17
  t11: ch = X86ISD::RET_GLUE t10, TargetConstant:i32<0>, Register:i8 $al, t10:1
```
Earlier transform is mentioned here
https://github.com/llvm/llvm-project/pull/113098#discussion_r1810307663

---------

Co-authored-by: mattarde <mattarde@intel.com>
2024-10-30 16:17:25 +08:00
David Green
f358422268 [Attributor] Add nofpclass test for phi+select recurrences. NFC 2024-10-30 08:10:35 +00:00
Boaz Brickner
9c8dab018d
[clang] Update the lifetimebound example with up-to-date expected warning and change the sample code to be a fully working example (#113437)
Tested the code: https://godbolt.org/z/n5xcq65YM
Tested the generated documentation:
![BruDQ2UkTXHA9PE](https://github.com/user-attachments/assets/cf527d1a-ef3b-41f2-84c2-4ca38af16d2d)
2024-10-30 08:59:49 +01:00
Nagy-Egri Máté Ferenc
362273d143
[clang-format] Fix path expansion inside git-clang-format.bat (#114078)
The trampoline script used on Windows (due to the absence of shebang
support) doesn't properly expand the path to the Python script, as it
leaves out the drive letter.

Functionally equivalent reproducer in action
```
PS C:\Users\mate> gc (gcm git-clang-formatish.bat).Source
@ECHO OFF
echo "%~pn0" %*
PS C:\Users\mate> git-clang-formatish
"\Users\mate\git-clang-formatish"
```

Adding `d` to the variable modifiers [as per the
docs](https://learn.microsoft.com/en-us/windows-server/administration/windows-commands/for)
the drive letter is added. Even in the magical cases when it works.

(I couldn't reproduce, but I suspect it's only tested from some
bash/cygwin variant, where the path becomes `/c/Program Files/...`, but
the drive letter is needed. Without it, I also observed cases when used
via `git clang-format` (without the inital dash) it tries to infer the
drive letter based on the current working directory. In that case it
fails to find `D:\Program Files\LLVM\bin\clang-format.exe`, which
naturally fails, because `Program Files` is on `C:`)
2024-10-30 00:51:11 -07:00
serge-sans-paille
dc56a86b96
[clang] Fix 71315698c9 in presence of incomplete types (#114095)
Incomplete types are not considered trivially copyable by clang but we
don't want to warn about invalid argument for memcpy / memset in that
case because we cannot prove they are not Trivially Copyable.
2024-10-30 07:32:05 +00:00
Congcong Cai
5df84a7535
[NFC] clean space in clang release note (#114188) 2024-10-30 14:37:04 +08:00
Congcong Cai
cad09404cc
[sema] enhance error handling for compound stmt body in StmtExpr (#113760)
Mark the whole StmtExpr invalid when the last statement in compound
statement is invalid.
Because the last statement need to do copy initialization, it causes
subsequent errors to simply ignore last invalid statement.

Fixed: #113468
2024-10-30 14:34:19 +08:00
Akshat Oke
44d0e9522a
[CodeGen][NewPM] Port TailDuplicate pass to NPM (#113293) 2024-10-30 11:48:40 +05:30
Ryosuke Niwa
b47e2316bf
[alpha.webkit.UncountedLocalVarsChecker] Warn the use of a raw pointer/reference when the guardian variable gets mutated. (#113859)
This checker has a notion of a guardian variable which is a variable and
keeps the object pointed to by a raw pointer / reference in an inner
scope alive long enough to "guard" it from use-after-free. But such a
guardian variable fails to flawed to keep the object alive if it ever
gets mutated within the scope of a raw pointer / reference.

This PR fixes this bug by introducing a new AST visitor class,
GuardianVisitor, which traverses the compound statements of a guarded
variable (raw pointer / reference) and looks for any operator=, move
constructor, or calls to "swap", "leakRef", or "releaseNonNull"
functions.
2024-10-29 23:13:23 -07:00
donald chen
df0d249b65
[mlir] [linalg] fix side effect of linalg op (#114045)
Linalg op need to take into account memory side effects happening inside
the region when determining their own side effects.

This patch fixed issue
https://github.com/llvm/llvm-project/issues/112881
2024-10-30 14:01:49 +08:00
Yingwei Zheng
f1467b3f73
[SDAG][NFC] Convert SDNodeFlags into an enumeration (#114167)
This patch converts `SDNodeFlags` into an enumeration as we did for
`FastMathFlags`. It simplifies the implementation and improves
compile-time. This patch is NFC since it doesn't break SDNodeFlags API.
2024-10-30 13:59:56 +08:00
Craig Topper
e7262c15d3
[RISCV] Add OperandType for sew and vecpolicy operands. (#114168) 2024-10-29 22:34:47 -07:00
Santhosh Kumar Ellendula
62ff85f079
[lldb-dap] Fix for missing 'raw_string_ostream::flush' removal in ProgressEvent.cpp; addressing #108745 (#114087)
I hope it was missed unintentionally, pushing the same for the review.
Ref: https://github.com/llvm/llvm-project/pull/108745

---------

Co-authored-by: Santhosh Kumar Ellendula <sellendu@hu-sellendu-hyd.qualcomm.com>
Co-authored-by: Santhosh Kumar Ellendula <sellendu@hu-sellendu-lv.qualcomm.com>
2024-10-30 10:50:59 +05:30
Matt Arsenault
6d9fc1b846
AMDGPU: Fix producing invalid IR on vector typed getelementptr (#114113)
This did not consider the IR change to allow a scalar base with a vector
offset part. Reject any users that are not explicitly handled.

In this situation we could handle the vector GEP, but that is a larger
change. This just avoids the IR verifier error by rejecting it.
2024-10-29 22:14:24 -07:00
Teresa Johnson
bb3915149a
[MemProf] Support for random hotness when writing profile (#113998)
Add support for generating random hotness in the memprof profile writer,
to be used for testing. The random seed is printed to stderr, and an
additional option enables providing a specific seed in order to
reproduce a particular random profile.
2024-10-29 22:10:33 -07:00
Shilei Tian
9a7519fdb3 Revert "[NFC][AMDGPU][Attributor] Exit earlier if entry CC (#114177)"
This reverts commit 922a0d3dfe2db7a2ef50e8cef4537fa94a7b95bb.
2024-10-30 00:53:43 -04:00
Shilei Tian
922a0d3dfe
[NFC][AMDGPU][Attributor] Exit earlier if entry CC (#114177)
Avoid calling TTI or other stuff unnecessarily
2024-10-30 00:42:44 -04:00
Craig Topper
f672cc1ee1
[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163) 2024-10-29 21:23:31 -07:00
Mel Chen
8420dbf2b9
[VPlan] Refine the constructor of VPWidenIntrinsicRecipe. nfc (#113890)
Infers member MayReadFromMemory, MayWriteToMemory, and
MayHaveSideEffects based on intrinsic attributes.

---------

Co-authored-by: Florian Hahn <flo@fhahn.com>
2024-10-30 12:22:28 +08:00