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3 Commits

Author SHA1 Message Date
Bill Schmidt
e09d4fd769 Add -mattr=+altivec and remove XFAIL. 
llvm-svn: 165666
 2012-10-10 22:25:11 +00:00
Bill Schmidt
6d110a5139 XFAIL for all targets pending investigation 
llvm-svn: 165664
 2012-10-10 21:52:10 +00:00
Bill Schmidt
b9bc47409d When generating spill and reload code for vector registers on PowerPC, 
the compiler makes use of GPR0.  However, there are two flavors of
GPR0 defined by the target:  the 32-bit GPR0 (R0) and the 64-bit GPR0
(X0).  The spill/reload code makes use of R0 regardless of whether we
are generating 32- or 64-bit code.

This patch corrects the problem in the obvious manner, using X0 and
ADDI8 for 64-bit and R0 and ADDI for 32-bit.

llvm-svn: 165658
 2012-10-10 21:25:01 +00:00