15498 Commits

Author SHA1 Message Date
Jinsong Ji
bf544fa1c3 Revert "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"
This reverts commit adffce71538e219aab4eeb024819baa7687262ff.

This is breaking test-suite, revert while investigation.
2020-07-27 21:07:00 +00:00
Jinsong Ji
adffce7153 [PowerPC] Remove QPX/A2Q BGQ/BGP CNK support
Per RFC http://lists.llvm.org/pipermail/llvm-dev/2020-April/141295.html
no one is making use of QPX/A2Q/BGQ/BGP CNK anymore.

This patch remove the support of QPX/A2Q in llvm, BGQ/BGP in clang,
CNK support in openmp/polly.

Reviewed By: hfinkel

Differential Revision: https://reviews.llvm.org/D83915
2020-07-27 19:24:39 +00:00
Shinji Okumura
bef19abcf7 [Attributor][NFC] Add tests to noalias.ll
Summary: Add tests to `noalias.ll` to make changes in D84665 clear

Reviewers: jdoerfert, sstefan1, uenoku, homerdin, baziotis

Subscribers: uenoku, kuter, bbn, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D84688
2020-07-28 03:53:06 +09:00
Roman Lebedev
1da9834557
[JumpThreading] ProcessBranchOnXOR(): bailout if any pred ends in indirect branch (PR46857)
SplitBlockPredecessors() can not split blocks that have such terminators,
and in two other places we already ensure that we don't end up calling
SplitBlockPredecessors() on such blocks. Do so in one more place.

Fixes https://bugs.llvm.org/show_bug.cgi?id=46857
2020-07-27 15:39:03 +03:00
Sanjay Patel
1ebcf03551 [InstSimplify] add tests for min/max intrinsics; NFC 2020-07-27 08:26:27 -04:00
Juneyoung Lee
6701c0bf73 [JumpThreading] Add a test case that has a phi with undef; NFC 2020-07-27 19:08:45 +09:00
Juneyoung Lee
c891f519e1 [JumpThreading] Add a test that threads jumps with frozen branch conditions 2020-07-27 19:04:50 +09:00
Juneyoung Lee
e1eacf27c6 [InstCombine] Fold freeze into phi if one operand is not undef
This patch adds folding freeze into phi if it has only one operand to target.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D84601
2020-07-27 17:07:27 +09:00
Juneyoung Lee
194a4beedd [InstCombine] Add more tests to freeze-phi.ll; NFC 2020-07-27 09:43:00 +09:00
Juneyoung Lee
ab4e1be7ab [InstCombine] Add a test for folding freeze into phi; NFC 2020-07-27 02:24:00 +09:00
Sanjay Patel
0481e1ae3c [InstSimplify] fold integer min/max intrinsics with limit constant 2020-07-26 09:41:54 -04:00
Sanjay Patel
c6cf71107a [InstSimplify] add tests for min/max intrinsics; NFC 2020-07-26 09:04:37 -04:00
Sanjay Patel
b89ae102e6 [InstSimplify] fold fcmp using isKnownNeverInfinity + isKnownNeverNaN
Follow-up to D84035 / rG7393d7574c09.
This sidesteps a question of FMF/poison on fcmp raised in PR46077:
http://bugs.llvm.org/PR46077

https://alive2.llvm.org/ce/z/TCsyzD
  define i1 @src(float %x) {
  %0:
    %x42 = fadd nnan ninf float %x, 42.000000
    %r = fcmp ueq float %x42, inf
    ret i1 %r
  }
  =>
  define i1 @tgt(float %x) {
  %0:
    ret i1 0
  }
  Transformation seems to be correct!

https://alive2.llvm.org/ce/z/FQaH7a
  define i1 @src(i8 %x) {
  %0:
    %cast = uitofp i8 %x to float
    %r = fcmp one float inf, %cast
    ret i1 %r
  }
  =>
  define i1 @tgt(i8 %x) {
  %0:
    ret i1 1
  }
  Transformation seems to be correct!
2020-07-26 09:04:37 -04:00
Sanjay Patel
912e9e5262 [InstSimplify] add tests for fcmp with infinity constant; NFC 2020-07-26 09:04:36 -04:00
Juneyoung Lee
920e267974 [JumpThreading] Add a test for D84598; NFC 2020-07-26 22:00:01 +09:00
Juneyoung Lee
9f074214b7 [ValueTracking] Instruction::isBinaryOp should be used for constexprs
This is a simple patch that makes canCreateUndefOrPoison use
Instruction::isBinaryOp because BinaryOperator inherits Instruction.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D84596
2020-07-26 21:48:51 +09:00
Juneyoung Lee
02dadab1b4 NFC; add an example that subtracts pointers to two global vars 2020-07-26 20:47:33 +09:00
Nikita Popov
f4199b8f0b [SCCP] Add assume non null test (NFC) 2020-07-25 16:02:15 +02:00
Nikita Popov
ad16e71c95 Reapply [SCCP] Directly remove non-feasible edges
Reapply with DTU update moved after CFG update, which is a
requirement of the API.

-----

Non-feasible control-flow edges are currently removed by replacing
the branch condition with a constant and then calling
ConstantFoldTerminator. This happens in a rather roundabout manner,
by inspecting the users (effectively: predecessors) of unreachable
blocks, and further complicated by the need to explicitly materialize
the condition for "forced" edges. I would like to extend SCCP to
discard switch conditions that are non-feasible based on range
information, but this is incompatible with the current approach
(as there is no single constant we could use.)

Instead, this patch explicitly removes non-feasible edges. It
currently only needs to handle the case where there is a single
feasible edge. The llvm_unreachable() branch will need to be
implemented for the aforementioned switch improvement.

Differential Revision: https://reviews.llvm.org/D84264
2020-07-25 14:52:35 +02:00
Florian Hahn
3c1476d26c [IPSCCP] Drop argmemonly after replacing pointer argument.
This patch updates IPSCCP to drop argmemonly and
inaccessiblemem_or_argmemonly if it replaces a pointer argument.

Fixes PR46717.

Reviewers: efriedma, davide, nikic, jdoerfert

Reviewed By: efriedma, jdoerfert

Differential Revision: https://reviews.llvm.org/D84432
2020-07-25 11:52:14 +01:00
Rong Xu
1dd39b1133 [PGO] Fix incorrect function entry count
Function entry count might be zero after the profile counts reset and
before reentry to the function.

Zero profile entry count is very bad as the profile count from BFI will
be wrong.

A simple fix is to set the profile entry count to 1 if there are
non-zero profile counts in this function.

Differential Revision: https://reviews.llvm.org/D84378
2020-07-24 17:39:55 -07:00
Rong Xu
31bd15c562 [PGO][InstrProf] Do not promote count if the exit blocks contains ret instruction
Skip profile count promotion if any of the ExitBlocks contains a ret
instruction. This is to prevent dumping of incomplete profile -- if the
the loop is a long running loop and dump is called in the middle
of the loop, the result profile is incomplete.

ExitBlocks containing a ret instruction is an indication of a long running
loop -- early exit to error handling code.

Differential Revision: https://reviews.llvm.org/D84379
2020-07-24 17:38:31 -07:00
Rong Xu
dcf1bca0de Revert "[PGO][InstrProf] Do not promote count if the exit blocks contains ret instruction"
This reverts commit 867ef4472d8e57384c929e4f06b74d1ac8883a99.
2020-07-24 17:33:49 -07:00
Rong Xu
867ef4472d [PGO][InstrProf] Do not promote count if the exit blocks contains ret instruction
Forgot including the tests in the commit 6fdc6f6c7d34af60c4.
2020-07-24 17:23:33 -07:00
Johannes Doerfert
aa09db495a [SROA] Teach promote to register about droppable instructions
This is the second of two patches to address PR46753. We basically allow
SROA to promote allocas that are used in doppable instructions, for
now that means `llvm.assume`. The (transitive) uses are replaced by
`undef` in the droppable instructions.

See also D83976.

Reviewed By: Tyker

Differential Revision: https://reviews.llvm.org/D83978
2020-07-24 15:15:39 -05:00
Johannes Doerfert
ce8928f2e4 [Mem2Reg] Teach promote to register about droppable instructions
This is the first of two patches to address PR46753. We basically allow
mem2reg to promote allocas that are used in doppable instructions, for
now that means `llvm.assume`. The uses of the alloca (or a bitcast or
zero offset GEP from there) are replaced by `undef` in the droppable
instructions.

Reviewed By: Tyker

Differential Revision: https://reviews.llvm.org/D83976
2020-07-24 15:15:38 -05:00
Johannes Doerfert
ce2d69b557 [SROA][Mem2Reg] Do not crash on alloca + addrspacecast
SROA knows that it can look through addrspacecast but
PromoteMemoryToRegister did not handle them. This caused an assertion
error for the test case, exposed while running
`Transforms/PhaseOrdering/inlining-alignment-assumptions.ll` with D83978
applied.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D84085
2020-07-24 15:15:38 -05:00
Arthur Eubanks
9bb6ce78be Rename scoped-noalias -> scoped-noalias-aa
Summary: To match NewPM name. Also the new name is clearer and more consistent.

Subscribers: jvesely, nhaehnle, hiraditya, asbirlea, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D84542
2020-07-24 12:14:27 -07:00
Roman Lebedev
3319d05630
[NFC][GVN] Improve loadpre-missed-opportunity.ll test again thanks to @fhahn 2020-07-24 20:32:51 +03:00
Florian Hahn
1c7c69c795 [ValueTracking] Check for ConstantExpr before using recursive helpers.
Make sure we do not call
constainsConstantExpression/containsUndefElement on ConstantExpression,
which is not supported.

In particular, containsUndefElement/constainsConstantExpression are only
supported on constants which are supported by getAggregateElement.

Unfortunately there's no convenient way to check if a constant supports
getAggregateElement, so just check for non-constantexpressions with
vector type. Other users of those functions do so too.

Reviewers: spatel, nikic, craig.topper, lebedev.ri, jdoerfert, aqjune

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D84512
2020-07-24 17:37:09 +01:00
Roman Lebedev
804622053a
[NFC][GVN] Clean loadpre-missed-opportunity.ll test some more 2020-07-24 12:44:22 +03:00
Florian Hahn
2c1799f892 [IPSCCP] Add another test case with argmemonly callsite attributes. 2020-07-24 10:13:51 +01:00
Fangrui Song
4637daa990 Revert D84264 "[SCCP] Directly remove non-feasible edges" & 5db5b4bc4394ca247c9eb665e03b851848aa2fbf
It breaks stage-2 build. Clang crashed when compiling
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp

llvm/Support/GenericDomTree.h eraseNode: Node is not a leaf node
2020-07-23 17:51:48 -07:00
Roman Lebedev
0a5971139a
[NFC][GVN] Add a (horrible) test for D84181 demonstrating non-NFC'ness 2020-07-24 01:28:23 +03:00
Sidharth Baveja
38a8217931 [Loop Fusion] Integrate Loop Peeling into Loop Fusion (re-land after fixing ASAN build failures)
This patch adds the ability to peel off iterations of the first loop in loop
fusion. This can allow for both loops to have the same trip count, making it
legal for them to be fused together.

Here is a simple scenario peeling can be used in loop fusion:

for (i = 0; i < 10; ++i)
  a[i] = a[i] + 3;
for (j = 1; j < 10; ++j)
  b[j] = b[j] + 5;

Here is we can make use of peeling, and then fuse the two loops together. We
can peel off the 0th iteration of the loop i, and then combine loop i and j for
i = 1 to 10.

a[0] = a[0] +3;
for (i = 1; i < 10; ++i) {
  a[i] = a[i] + 3;
  b[i] = b[i] + 5;
}

Currently peeling with loop fusion is only supported for loops with constant
trip counts and a single exit point. Both unguarded and guarded loops are
supported.

Reviewed By: bmahjour (Bardia Mahjour), MaskRay (Fangrui Song)

Differential Revision: https://reviews.llvm.org/D82927
2020-07-23 21:02:04 +00:00
Nikita Popov
183342c0a9 [SCCP] Add another switch+phi test (NFC) 2020-07-23 21:51:09 +02:00
Nikita Popov
9394c3ec88 [SCCP] Directly remove non-feasible edges
Non-feasible control-flow edges are currently removed by replacing
the branch condition with a constant and then calling
ConstantFoldTerminator. This happens in a rather roundabout manner,
by inspecting the users (effectively: predecessors) of unreachable
blocks, and further complicated by the need to explicitly materialize
the condition for "forced" edges. I would like to extend SCCP to
discard switch conditions that are non-feasible based on range
information, but this is incompatible with the current approach
(as there is no single constant we could use.)

Instead, this patch explicitly removes non-feasible edges. It
currently only needs to handle the case where there is a single
feasible edge. The llvm_unreachable() branch will need to be
implemented for the aforementioned switch improvement.

Differential Revision: https://reviews.llvm.org/D84264
2020-07-23 20:32:57 +02:00
Nikita Popov
def48b0e88 [PredicateInfo][SCCP] Remove assertion (PR46814)
As long as RenamedOp is not guaranteed to be accurate, we cannot
assert here and should just return false. This was already done
for the other conditions in this function.

Fixes https://bugs.llvm.org/show_bug.cgi?id=46814.
2020-07-23 19:36:51 +02:00
Florian Hahn
0f80d598b0 [IPSCCP] Add test case for PR46717 for argmemonly handling. 2020-07-23 17:25:26 +01:00
Sanjay Patel
cfe40acd16 [VectorCombine] add tests for load vectorization; NFC 2020-07-23 11:24:04 -04:00
Florian Hahn
82e35197e6 [LSR] Re-generate check lines for test.
The test is quite frafile, as the check lines match IR numbers and it is
not obvious why only a very small subset is checked.

Re-generate check lines, so further changes are more obvious.
2020-07-23 13:53:53 +01:00
Florian Hahn
09c96a31ef [LoopIdiom] Add additional test cases. 2020-07-23 13:53:26 +01:00
Hamilton Tobon Mosquera
6f0d99d2b9 [OpenMPOpt] Regression test for hiding latency of H2D mem transfers 2020-07-22 20:02:54 -05:00
Fangrui Song
27650ec554 Revert D81682 "[PGO] Extend the value profile buckets for mem op sizes."
This reverts commit 4a539faf74b9b4c25ee3b880e4007564bd5139b0.

There is a __llvm_profile_instrument_range related crash in PGO-instrumented clang:

```
(gdb) bt
llvm::ConstantRange const&, llvm::APInt const&, unsigned int, bool) ()
llvm::ScalarEvolution::getRangeForAffineAR(llvm::SCEV const*, llvm::SCEV
const*, llvm::SCEV const*, unsigned int) ()
```

(The body of __llvm_profile_instrument_range is inlined, so we can only find__llvm_profile_instrument_target in the trace)

```
 23│    0x000055555dba0961 <+65>:    nopw   %cs:0x0(%rax,%rax,1)
 24│    0x000055555dba096b <+75>:    nopl   0x0(%rax,%rax,1)
 25│    0x000055555dba0970 <+80>:    mov    %rsi,%rbx
 26│    0x000055555dba0973 <+83>:    mov    0x8(%rsi),%rsi  # %rsi=-1 -> SIGSEGV
 27│    0x000055555dba0977 <+87>:    cmp    %r15,(%rbx)
 28│    0x000055555dba097a <+90>:    je     0x55555dba0a76 <__llvm_profile_instrument_target+342>
```
2020-07-22 16:08:25 -07:00
Rong Xu
50da55a585 [PGO] Supporting code for always instrumenting entry block
This patch includes the supporting code that enables always
instrumenting the function entry block by default.

This patch will NOT the default behavior.

It adds a variant bit in the profile version, adds new directives in
text profile format, and changes llvm-profdata tool accordingly.

This patch is a split of D83024 (https://reviews.llvm.org/D83024)
Many test changes from D83024 are also included.

Differential Revision: https://reviews.llvm.org/D84261
2020-07-22 15:01:53 -07:00
Nikita Popov
e20b3079c1 [SCCP] Add additional multi-edge + phi tests (NFC) 2020-07-22 22:10:23 +02:00
Nikita Popov
33f6542014 [SCCP] Regenerate test checks (NFC)
And adjust the indbrtest4 test to actually test what it's supposed
to. BB1 is supposed to be eliminated here, but isn't, because
BB0 still branches to it. This was lost due to the incomplete CHECK
lines.
2020-07-22 22:10:23 +02:00
Nikita Popov
eae6bb3807 [SCCP] Add multi-edge switch + phi test case (NFC) 2020-07-22 20:28:22 +02:00
Anton Afanasyev
56c92bf4b7 [SLP][Test] Precommit tests for D83779. NFC. 2020-07-22 18:25:45 +03:00
Sebastian Neubauer
2a6c871596 [InstCombine] Move target-specific inst combining
For a long time, the InstCombine pass handled target specific
intrinsics. Having target specific code in general passes was noted as
an area for improvement for a long time.

D81728 moves most target specific code out of the InstCombine pass.
Applying the target specific combinations in an extra pass would
probably result in inferior optimizations compared to the current
fixed-point iteration, therefore the InstCombine pass resorts to newly
introduced functions in the TargetTransformInfo when it encounters
unknown intrinsics.
The patch should not have any effect on generated code (under the
assumption that code never uses intrinsics from a foreign target).

This introduces three new functions:
TargetTransformInfo::instCombineIntrinsic
TargetTransformInfo::simplifyDemandedUseBitsIntrinsic
TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic

A few target specific parts are left in the InstCombine folder, where
it makes sense to share code. The largest left-over part in
InstCombineCalls.cpp is the code shared between arm and aarch64.

This allows to move about 3000 lines out from InstCombine to the targets.

Differential Revision: https://reviews.llvm.org/D81728
2020-07-22 15:59:49 +02:00