281800 Commits

Author SHA1 Message Date
Deric Cheung
2656928d0c
Reland "[HLSL] Implement the reflect HLSL function" (#123853)
This PR relands
[#122992](https://github.com/llvm/llvm-project/pull/122992).

Some machines were failing to run the `reflect-error.ll` test due to the
RUN lines
```llvm
; RUN: not %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o /dev/null 2>&1 -filetype=obj %}
; RUN: not %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o /dev/null 2>&1 -filetype=obj %}
```
which failed when `spirv-tools` was not present on the machine due to
running the command `not` without any arguments.

These RUN lines have been removed since they don't actually test
anything new compared to the other two RUN lines due to the expected
error during instruction selection.
```llvm
; RUN: not llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
; RUN: not llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
```
2025-01-22 13:29:19 -08:00
Brox Chen
18e9d3dbe5
[AMDGPU][True16][MC] true16 for v_cmpx_xx_u/i16 (#123424)
A bulk commit of true16 support for v_cmp_xx_i/u16 instructions
including:

v_cmpx_lt_i16
v_cmpx_eq_i16
v_cmpx_le_i16
v_cmpx_gt_i16
v_cmpx_ne_i16
v_cmpx_ge_i16
v_cmpx_lt_u16
v_cmpx_eq_u16
v_cmpx_le_u16
v_cmpx_gt_u16
v_cmpx_ne_u16
v_cmpx_ge_u16
2025-01-22 15:57:16 -05:00
Brox Chen
1cf0af3d32
[AMDGPU][True16][MC] true16 for v_cmpx_class_f16 (#123251)
True16 format for v_cmpx_class_f16. Update VOPCX_CLASS t16 and fake16
pseudo.
2025-01-22 15:56:58 -05:00
Teresa Johnson
7ad8a3da47
[MemProf] Simplify edge iterations (NFC) (#123469)
Remove edge iterator parameters from the various helpers that move edges
onto other nodes, and their associated iterator update code, and instead
iterate over copies of the edge lists in the caller loops. This also
avoids the need to increment these iterators at every early loop
continue.

This simplifies the code, makes it less error prone when updating, and
in particular, facilitates adding handling of recursive contexts.

There were no measurable compile time and memory overhead effects for a
large target.
2025-01-22 11:35:52 -08:00
Michael Maitland
1687aa2a99
[RISCV][VLOPT] Don't reduce the VL is the same as CommonVL (#123878)
This fixes the slowdown in #123862.
2025-01-22 13:49:54 -05:00
Stefan Pintilie
340706f311
[PowerPC] Fix saving of Link Register when using ROP Protect (#123101)
An optimization was added that tries to move the uses of the mflr
instruction away from the instruction itself. However, this doesn't work
when we are using the hashst instruction because that instruction needs
to be run before the stack frame is obtained.

This patch disables moving instructions away from the mflr in the case
where ROP protection is being used.

---------

Co-authored-by: Lei Huang <lei@ca.ibm.com>
2025-01-22 13:44:20 -05:00
Philip Reames
589593254e
[RISCV][VLOpt] Reorganize visit order and worklist management (#123973)
This implements a suggestion by Craig in PR #123878. We can move the
worklist management out of the per-instruction work and do it once at
the end of scanning all the instructions. This should reduce repeat
visitation of the same instruction when no changes can be made.

Note that this does not remove the inherent O(N^2) in the algorithm.
We're still potentially visiiting every user of every def.

I also included a guard for unreachable blocks since that had been
mentioned as a possible cause. It seems we've rulled that out, but
guarding for this case is still a good idea.
2025-01-22 10:42:15 -08:00
Jon Roelofs
ec15b24250
[llvm][Support] Only enable backtrace test when it's enabled (#123852)
rdar://138554797
2025-01-22 10:37:56 -08:00
Craig Topper
146ee98caa
[RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (#123865)
We had two WriteRes for WriteJalr with difference latencies. Drop the
duplicate and change the latency of Jal to 1 based on review feedback
2025-01-22 10:37:01 -08:00
Julian Nagele
137d706739
[SCEV] Do not attempt to collect loop guards for loops without predecessor. (#123662)
Attempting to collect loop guards for loops without a predecessor can
lead to non-terminating recursion trying to construct a SCEV.

Fixes https://github.com/llvm/llvm-project/issues/122913.
2025-01-22 18:36:37 +00:00
Kazu Hirata
b40739a6e9 Revert "[LLVM][Clang][AArch64] Implement AArch64 build attributes (#118771)"
This reverts commit d7fb4a275c98f4035d1083b5eb3edd2ffb2da00e.

Buildbots failing:
https://lab.llvm.org/buildbot/#/builders/169/builds/7671
https://lab.llvm.org/buildbot/#/builders/65/builds/11046
2025-01-22 10:12:27 -08:00
goldsteinn
a56ba1fab0
[ValueTracking] Handle recursive select/PHI in ComputeKnownBits (#114689)
Finish porting #114008 to `KnownBits` (Follow up to #113707).
2025-01-22 11:51:18 -06:00
Ellis Hoag
b1943f40e7
[BranchFolding] Remove getBranchDebugLoc() (#114613) 2025-01-22 09:50:49 -08:00
Thurston Dang
2476417232
Reapply "[sanitizer][NFCI] Add Options parameter to LowerAllowCheckPass" (#122833) (#122994)
This reverts commit 1515caf7a59dc20cb932b724b2ef5c1d1a593427
(https://github.com/llvm/llvm-project/pull/122833) i.e., relands
7d8b4eb0ead277f41ff69525ed807f9f6e227f37
(https://github.com/llvm/llvm-project/pull/122765), with LowerAllowCheckPass::Options moved inside the callback to fix a stack use-after-scope error.

---------

Co-authored-by: Vitaly Buka <vitalybuka@gmail.com>
2025-01-22 09:32:12 -08:00
Simon Pilgrim
44f3168110 [X86] vector reduction tests - regenerate VPTERNLOG comments 2025-01-22 17:23:37 +00:00
Simon Pilgrim
a25f2cb3e6 [X86] vector rotate tests - regenerate VPTERNLOG comments 2025-01-22 17:23:37 +00:00
Simon Pilgrim
bb754f2c98 [X86] avx512 intrinsics tests - regenerate VPTERNLOG comments 2025-01-22 17:23:37 +00:00
Simon Pilgrim
e6c7d6a56a [X86] avx512-broadcast-unfold.ll - regenerate VPTERNLOG comments 2025-01-22 17:23:37 +00:00
Simon Pilgrim
603529b29e [X86] add/sub signed sat vec tests - regenerate VPTERNLOG comments 2025-01-22 17:23:36 +00:00
Simon Pilgrim
16298e4cf2 [X86] var-permute-256.ll - regenerate VPTERNLOG comments 2025-01-22 17:23:36 +00:00
Craig Topper
9e6494c0fb
[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC (#123799)
This holds a physical register unit or virtual register and mask.

While I was here I've used emplace_back and removed an unneeded use of a
template.
2025-01-22 09:11:22 -08:00
Craig Topper
13d09dfad6
[X86] Simplify ArrayRef construction. NFC (#123899)
I think the std::begin/end were to work around an old gcc bug. Hopefully
we don't need them anymore.
2025-01-22 09:07:58 -08:00
Jon Roelofs
75ce2dc475
[llvm][AArch64] apple-m4 does not have FEAT_{SPEv1p2,SEL2,MPAM} (#123827)
This commit addresses some uncertainty raised in 84fa1755a5b7845ddaeaa513a3786013c76c9c88 as to which features Apple M4 has.
2025-01-22 09:00:02 -08:00
Fangrui Song
58c6d440f8
[CMake] Remove HAVE_DLFCN_H and HAVE_DLADDR (#123879)
It is sufficient to just use `HAVE_DLOPEN`.
2025-01-22 08:15:10 -08:00
Joshua Cranmer
b0d35cf22e
[SSAUpdater] Avoid scanning basic blocks to find instruction order. (#123803)
This fixes a compile-time regression caused by #116645, where an entry
basic block with a very large number of allocas and other instructions
caused SROA to take ~100× its expected runtime, as every alloca (with ~2
uses) now calls this method to find the order of those few instructions,
rescanning the very large basic block every single time.

Since this code was originally written, Instructions now have ordering
numbers available to determine relative order without unnecessarily
scanning the basic block.
2025-01-22 11:11:41 -05:00
Matt Arsenault
93d35ad5f5
AMDGPU: Delete FillMFMAShadowMutation (#123861)
No test changes with this removed and it appears to
be obsolete.
2025-01-22 22:41:25 +07:00
Danial Klimkin
c938436f71
Revert "[GISel] Add more FP opcodes to CSE (#123624)" (#123954)
This reverts commit 43177b524ee06dfc09cbc357ff277d4f53f5dc15.
2025-01-22 16:21:05 +01:00
Nico Weber
d0a89e7179 [gn] fix mistake in d7fb4a275c98f 2025-01-22 10:19:30 -05:00
Nico Weber
4170d6123c [gn] port 6aeffcdb9130 2025-01-22 10:16:53 -05:00
Joseph Huber
70a16b90ff
[HIP] Support managed variables using the new driver (#123437)
Summary:
Previously, managed variables didn't work in rdc mode using the new
driver because we just didn't register them. This was previously ignored
because we didn't have enough space in the current struct format. This
patch amends that by just emitting a struct pair for the two variables
and using the single pointer.

In the future, a more extensible entry format would be nice, but that
can be done later.
2025-01-22 09:13:14 -06:00
Phoebe Wang
4f40b07533
[X86][AVX10.2-SATCVT][NFC] Remove NE from intrinsic and instruction name (#123275)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2025-01-22 22:53:47 +08:00
Alexey Bataev
ccd77953d0 [SLP][NFC]Add a test with potential alternate node, marked for minbitwidth size 2025-01-22 06:48:34 -08:00
Yeaseen
d80eb928c7
[llvm] Remove undef from llvm/test/Transforms tests (#123889)
This PR replaces some instances of `undef` with `function argument
value` or `poison` or `concrete values` in several tests under
`llvm/test/Transforms/` directory. These changes align with modern LLVM
standards for better-defined behavior and test determinism. If this
small PR is okay and gets merged, I will work on the rest.

This is inspired by [this
project](https://discourse.llvm.org/t/gsoc-2024-remove-undefined-behavior-from-tests/77236/29),
work done on this by @leewei05
2025-01-22 14:47:15 +00:00
SivanShani-Arm
d7fb4a275c
[LLVM][Clang][AArch64] Implement AArch64 build attributes (#118771)
- Added support for AArch64-specific build attributes.
- Print AArch64 build attributes to assembly.
- Parse AArch64 build attributes from assembly.
- Emit AArch64 build attributes to ELF.

Specification:
 https://github.com/ARM-software/abi-aa/pull/230
2025-01-22 14:23:46 +00:00
lialan
43177b524e
[GISel] Add more FP opcodes to CSE (#123624)
This fixes #122724
2025-01-22 06:20:42 -08:00
Marc Auberer
5136c6d9d2
[Tools][Docker] Update Dockerfiles and Docker guide (#123841)
Fixes #123669

- Update Dockerfiles to work with the LLVM trunk
- Adapt Documentation accordingly
- Fix duplicate `-c` flag
2025-01-22 13:53:23 +01:00
Sushant Gokhale
c6c647588f
[SLP][NFC] Update test for PR #118055 (#122696)
This patch updates the motivating test for the above PR so that it does
not conflict with urem PR #122236
2025-01-22 03:28:34 -08:00
Pengcheng Wang
9d676e2cb6
[MCA] Use MCInstrAnalysis to analyse call/return instructions (#123882)
The flag set in `MCInstrDesc` is not accurate and we should use
the result of `MCInstrAnalysis`.
2025-01-22 19:10:28 +08:00
Wang Pengcheng
d03fab1be3 [RISCV] Add precommit test for #123882
Add MCA test for jump instructions.
2025-01-22 19:08:39 +08:00
Jay Foad
b7423e94be
[AMDGPU] Remove .i32 suffix from comments documenting intrinsics (#123919)
These intrinsics are overloaded. The documentation should not single out
the i32 overload.
2025-01-22 11:01:33 +00:00
Simon Pilgrim
58be6fd1b4 [X86] fixup-bw-inst.ll - regenerate test checks to simplify diff for #123787 2025-01-22 10:47:09 +00:00
Sander de Smalen
6b1db79887 Revert "Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" (#123632)"
There's a regression with one of the bootstrap builds for x86.
I'll revert this while I investigate.

This reverts commit 4df6d3df24ae9cff07c70c96a1663cbba6e1dca5.
2025-01-22 10:11:32 +00:00
David Sherwood
4a2ebd6661
[LV][NFC] Refactor structures used to maintain uncountable exit info (#123219)
I've removed the HasUncountableEarlyExit variable, since we can
already determine whether or not a loop has an early exit by seeing
if we found an uncountable exit.

I have also deleted the old UncountableExitingBlocks and
UncountableExitBlocks lists and replaced them with a single
uncountable edge. This means we don't need to worry about keeping the
list entries in sync and makes it clear which exiting block
corresponds to which exit block.
2025-01-22 09:40:08 +00:00
Alexey Merzlyakov
ef37c3dd03
[llvm][Docs] Release note for LLDB optionally disabled regsets for RV64 (#123363)
This PR adds the release note point for LLDB 20, discussed in
https://github.com/llvm/llvm-project/pull/104547#issuecomment-2587479877
for the same ticket

---------

Co-authored-by: David Spickett <david.spickett@linaro.org>
2025-01-22 09:30:13 +00:00
tangaac
dedf014901
[LoongArch] lower SCALAR_TO_VECTOR to INSERT_VECTOR_ELT (#122863)
```llvm
define <16 x i8> @scalar_to_16xi8(i8 %val) {
  %ret = insertelement <16 x i8> undef, i8 %val, i32 0
  ret <16 x i8> %ret
}
```

before
```asm
addi.d	$sp, $sp, -16
st.b	$a0, $sp, 0
vld	$vr0, $sp, 0
addi.d	$sp, $sp, 16
ret
```

after
```asm
vinsgr2vr.b $vr0, $a0, 0
ret
```

---------

Co-authored-by: Lu Weining <luweining@loongson.cn>
2025-01-22 17:27:52 +08:00
dlav-sc
0d24130008
[llvm][Docs] Add lldb user expressions related release notes (#123772) 2025-01-22 12:25:44 +03:00
Akshat Oke
a343b8e595
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695) 2025-01-22 14:54:01 +05:30
Sylvestre Ledru
d064d3fc2c
Revert "[Xtensa] Implement Windowed Register Option." (#123913)
Reverts llvm/llvm-project#121118
for causing #123817
2025-01-22 10:11:51 +01:00
Benjamin Maxwell
6e1ea7e5a7
[AArch64] Set the default streaming hazard size to 1024 for +sme,+sve (#123753)
The default for all other feature combinations remains at zero (i.e. no
streaming hazards). This value may be adjusted in the future (e.g. based
on the processor family), for now, it is set conservatively.
2025-01-22 09:08:17 +00:00
Sander de Smalen
4df6d3df24
Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" (#123632)
This PR aims to reland work done by @arsenm which was previously
reverted due to some tangentially related scheduler issues as discussed
on #76416.

This PR cherry-picks the original commit (0e46b49de433), and adds
another patch on top with the following changes:

* The code in `updateRegDefsUses` now updates subranges when
  subreg-liveness-tracking is enabled.

* When adding an implicit-def operand for the super-register,
  the code in `reMaterializeTrivialDef` which tries to remove
  undefined subranges should now take into account that the lanes
  from the super-reg are no longer undefined.

Co-authored-by: Matt Arsenault <Matthew.Arsenault@amd.com>
2025-01-22 09:07:46 +00:00