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Author	SHA1	Message	Date
zhijian lin	2cd32132db	[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863 ) This patch utilizes getReservedRegs() to find asm clobberable registers. And to make the result of getReservedRegs() accurate, this patch implements the todo, which is to make r2 allocatable on AIX for some leaf functions.	2024-11-04 12:57:26 -05:00
zhijian lin	a51712751c	[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943 ) Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.	2024-11-04 09:40:54 -05:00
Kai Luo	bfd3734610	[PowerPC] Use MIR test so that it's not affected by instruction selection. NFC.	2023-11-20 09:51:12 +00:00

Author

SHA1

Message

Date

zhijian lin

2cd32132db

[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863 )

This patch utilizes getReservedRegs() to find asm clobberable registers.
And to make the result of getReservedRegs() accurate, this patch
implements the todo, which is to make r2 allocatable on AIX for some
leaf functions.

2024-11-04 12:57:26 -05:00

zhijian lin

a51712751c

[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943 )

Utilize common API in PPCTargetParser
(https://github.com/llvm/llvm-project/pull/97541) to set default CPU
with same interfaces for LLC.
This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU
to ppc64.

2024-11-04 09:40:54 -05:00

Kai Luo

bfd3734610

[PowerPC] Use MIR test so that it's not affected by instruction selection. NFC.

2023-11-20 09:51:12 +00:00

3 Commits