5 Commits

Author SHA1 Message Date
Luke Lau
1cb599835c [RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC
In the vast majority of f16 tests we don't end up emitting any scalar
code that needs +zfh, so remove it.
2024-10-31 06:51:39 +08:00
Luke Lau
edac1b2d63
[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)
For f16 with zvfhmin, we promote most ops and VP ops to f32. This does
the same for bf16 with zvfbfmin, so the two fp types should now be in
sync.

There are a few places in the custom lowering where we need to check for
a LMUL 8 f16/bf16 vector that can't be promoted and must be split, this
extracts that out into isPromotedOpNeedingSplit.

In a follow up NFC we can deduplicate the code that sets up the
promotions.
2024-09-18 17:39:40 +08:00
Craig Topper
3055c5815a [RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
This has been ratified according to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions

Differential Revision: https://reviews.llvm.org/D155668
2023-07-19 10:03:57 -07:00
Jianjian GUAN
77da27b5e3 [RISCV] Improve selection for vector fpclass.
Since vfclass intruction will only set one single bit in the result, so if we only want to check 1 fp class, we could use vmseq to do it.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D151967
2023-06-06 10:24:24 +08:00
LiaoChunyu
477d1080cb [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v
After D149063.
This patch adds support for both scalable and fixed-length vector.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D151176
2023-05-26 14:44:35 +08:00