548 Commits

Author SHA1 Message Date
Brox Chen
5d1c596ab4
[AMDGPU][True16][MC] true16 for minimummaximum/max/min/max3/min3 (#124184)
true16 support for gfx12 instructions including:

v_minimummaximum_f16
v_maximumminimum_f16
v_maximum_f16
v_minimum_f16
v_maximum3_f16
v_minimum3_f16
2025-01-27 16:52:59 -05:00
Brox Chen
62340ff8d8
[AMDGPU][True16][MC] true16 for v_cmpx_xx_f16 (#123419)
A bulk commit of true16 support for v_cmpx_xx_f16 instructions
including:

v_cmpx_f_f16
v_cmpx_le_f16
v_cmpx_gt_f16
v_cmpx_lg_f16
v_cmpx_ge_f16
v_cmpx_o_f16
v_cmpx_u_f16
v_cmpx_nge_f16
v_cmpx_nlg_f16
v_cmpx_ngt_f16
v_cmpx_nle_f16
v_cmpx_neq_f16
v_cmpx_nlt_f16
v_cmpx_t_f16

v_cmpx_eq_f16 is not in this patch and will be added in the following
patch
2025-01-27 10:12:20 -05:00
Brox Chen
241e5d8c5c
[AMDGPU][True16][MC] true16 for v_cmpx_eq_f16 (#124038)
True16 format for v_cmpx_eq_f16.

Also cleaned up some stray gfx11 check line in gfx12 dasm test
2025-01-24 18:15:40 -05:00
Acim Maravic
7ddeea3598
[LLVM][AMDGPU] MC support for ds_bpermute_fi_b32 (#124108)
Added assembler/disassembler support for ds_bpermute_fi_b32 instruction,
as well as tests.
2025-01-23 17:55:00 +01:00
Brox Chen
18e9d3dbe5
[AMDGPU][True16][MC] true16 for v_cmpx_xx_u/i16 (#123424)
A bulk commit of true16 support for v_cmp_xx_i/u16 instructions
including:

v_cmpx_lt_i16
v_cmpx_eq_i16
v_cmpx_le_i16
v_cmpx_gt_i16
v_cmpx_ne_i16
v_cmpx_ge_i16
v_cmpx_lt_u16
v_cmpx_eq_u16
v_cmpx_le_u16
v_cmpx_gt_u16
v_cmpx_ne_u16
v_cmpx_ge_u16
2025-01-22 15:57:16 -05:00
Brox Chen
1cf0af3d32
[AMDGPU][True16][MC] true16 for v_cmpx_class_f16 (#123251)
True16 format for v_cmpx_class_f16. Update VOPCX_CLASS t16 and fake16
pseudo.
2025-01-22 15:56:58 -05:00
Brox Chen
e1c1e74a6f
[AMDGPU][True16][MC] true16 for v_cmp_class_f16 (#122984)
True16 format for v_cmp_class_f16. Update VOPC_CLASS t16 and fake16
pseudo.
2025-01-21 10:07:14 -05:00
Brox Chen
70632f9566
[AMDGPU][True16][MC] true16 for v_cmp_xx_f16 (#122943)
A bulk commit of true16 support for v_cmp_xx_f16 instructions including:
v_cmp_f_f16
v_cmp_eq_f16
v_cmp_le_f16
v_cmp_gt_f16
v_cmp_lg_f16
v_cmp_ge_f16
v_cmp_o_f16
v_cmp_u_f16
v_cmp_nge_f16
v_cmp_nlg_f16
v_cmp_ngt_f16
v_cmp_nle_f16
v_cmp_neq_f16
v_cmp_nlt_f16
v_cmp_t_f16

Added a GFX12 runline for fcmp.f16
2025-01-21 10:06:22 -05:00
Brox Chen
28ae363ec0
[AMDGPU][True16][MC] true16 for v_cmp_xx_i/u16 (#122968)
A bulk commit of true16 support for v_cmp_xx_i/u16 instructions
including:

v_cmp_lt_i16
v_cmp_eq_i16
v_cmp_le_i16
v_cmp_gt_i16
v_cmp_ne_i16
v_cmp_ge_i16
v_cmp_lt_u16
v_cmp_eq_u16
v_cmp_le_u16
v_cmp_gt_u16
v_cmp_ne_u16
v_cmp_ge_u16
2025-01-20 16:20:54 -05:00
Brox Chen
a18f4bdb18
[AMDGPU][True16][MC] true16 for v_cmpx_lt_f16 (#122936)
True16 format for v_cmpx_lt_f16. Update VOPCX t16 and fake16 pseudo.
2025-01-17 09:38:52 -05:00
Brox Chen
8a0c2e7567
[AMDGPU][True16][MC][CodeGen] true16 for v_cndmask_b16 (#119736)
Support true16 format for v_cndmask_b16 in MC and CodeGen in true16 and
fake16 flow.

Since we are replacing `v_cndmask_b16` to `v_cndmask_b16_t16/fake16`, we
have to at least update the fake16 codeGen to get codeGen test passing.
For this case, we have to update the true16 and with fake16 together,
otherwise some of the true16 tests will fail
2025-01-16 17:18:28 -05:00
Brox Chen
5e26ff35c1
[AMDGPU][True16][MC] true16 for v_cmp_lt_f16 (#122499)
True16 format for v_cmp_lt_f16. Update VOPC t16 and fake16 pseudo.
2025-01-14 10:03:36 -05:00
Brox Chen
9c85cdec4a
[AMDGPU][True16][MC][NFC]update vopc dasm test with latest update script (#122360)
This is a NFC. 

Update VOPC dasm test with +real-true16 and run latest update script.
2025-01-10 09:43:20 -05:00
Mirko Brkušanin
3def49cb64
[AMDGPU] Remove s_wakeup_barrier instruction (#122277) 2025-01-10 11:30:22 +01:00
Brox Chen
d0812dbbff
[AMDGPU][True16][MC] true16 for v_minmax/maxmin_f16 and v_minmax/maxmin_num_f16 (#120617)
True16 support for v_minmax/maxmin_f16(GFX11) and
v_minmax/maxmin_num_f16(GFX12).

These insts are updated at the same time since we are replacing the
`v_minmax/maxmin_f16` to `v_minmax/maxmin_fake16_f16` while
`v_minmax/maxmin_num_f16` are alias insts and share the same CodeGen
pattern.

Added a GFX12 runline in minmax.ll in fake16 flow
2025-01-07 10:27:54 -05:00
Brox Chen
4af3332015
[AMDGPU][True16][MC] true16 for v_cvt_u32_u16 (#120646)
Support true16 format for v_cvt_u32_u16 in MC
2025-01-06 15:28:48 -05:00
Brox Chen
ce831a231a
[AMDGPU][True16][MC] true16 for v_fma_f16 (#119477)
Support true16 format for v_fma_f16 in MC.

Since we are replacing v_fma_f16 to v_fma_f16_t16/v_fma_f16_fake16 in
Post-GFX11, have to update the CodeGen pattern for v_fma_f16_fake16 to
get CodeGen test passing. There is no pattern modified/created, but just
replacing the v_fma_f16 with fake16 format.
2025-01-06 15:02:04 -05:00
Brox Chen
d7acf03cec
[AMDGPU][True16][MC] true16 for v_rndne_f16 (#120691)
Support true16 format for v_rndne_b16 in MC
2025-01-03 16:32:15 -05:00
Brox Chen
bf274b3d80
[AMDGPU][True16][MC] true16 for v_cos_f16 (#120639)
Support true16 format for v_cos_f16 in MC
2025-01-03 15:46:41 -05:00
Brox Chen
b71a6fd042
[AMDGPU][True16][MC] true16 for v_cvt_i32_i16 (#120645)
Support true16 format for v_cvt_i32_i16 in MC
2025-01-03 15:46:06 -05:00
Brox Chen
dc307be1b5
[AMDGPU][True16][MC] true16 for v_fract_f16 (#120647)
Support true16 format for v_fract_f16 in MC
2025-01-03 15:45:33 -05:00
Jun Wang
b2adeae865
[AMDGPU][MC] Allow null where 128b or larger dst reg is expected (#115200)
For GFX10+, currently null cannot be used as dst reg in instructions
that expect the dst reg to be 128b or larger (e.g., s_load_dwordx4).
This patch fixes this problem while ensuring null cannot be used as S#,
T#, or V#.
2025-01-03 11:49:51 -08:00
Brox Chen
3b72c62e7f
[AMDGPU][True16][MC] true16 for v_frexp_mant_f16 (#120653)
Support true16 format for v_frexp_mant_f16 in MC
2025-01-03 14:42:39 -05:00
Brox Chen
34d2c3b934
[AMDGPU][True16][MC] true16 for v_sin_f16 (#120692)
Support true16 format for v_sin_f16 in MC
2025-01-03 14:11:25 -05:00
Brox Chen
d37aa5135c
[AMDGPU][True16][MC] true16 for v_not_b16 (#120659)
Support true16 format for v_not_b16 in MC
2025-01-03 13:09:23 -05:00
Brox Chen
e5acb167b7
[AMDGPU][True16][MC] true16 for v_trunc_f16 (#120693)
Support true16 format for v_trunc_f16 in MC
2025-01-03 11:43:45 -05:00
Brox Chen
322f16e624
[AMDGPU][True16][MC] true16 for v_sat_pk_u8_i16 (#120634)
Support true16 format for v_sat_pk_u8_i16 in MC
2025-01-03 11:43:07 -05:00
Brox Chen
8b23ebb498
[AMDGPU][True16[MC] true16 for v_max3/min3_num_f16 (#121510)
V_MAX3/MIN3_NUM_F16 are alias GFX12 instructions with V_MAX3/MIN3_F16 in
GFX11 and they should be updated together.

This fix a bug introduced in
https://github.com/llvm/llvm-project/pull/113603 such that only
V_MAX3/MIN3_F16 are replaced in true16 format. Also added GFX12 runlines
for CodeGen test
2025-01-03 08:55:58 +00:00
Brox Chen
4044886c7c
Revert "[AMDGPU][True16][MC] true16 for v_minmax/maxmin_f16 (#119586)" (#120594)
This reverts commit e0526b0780f56eede09b05a859a93626ecdc6e4d.

The `v_minmax/maxmin_f16`(GFX11) needs to be updated to t16 with
`v_minmax/maxmin_num_f16`(GFX12) together since they share the same
codegen pattern. Revert the old patch and resubmit
2024-12-19 12:10:23 -05:00
Brox Chen
e0526b0780
[AMDGPU][True16][MC] true16 for v_minmax/maxmin_f16 (#119586)
Support true16 format for v_minmax/maxmin_f16 in MC.

Since we are replacing `v_minmax/maxmin_f16` to `v_minmax/maxmin_f16_t16
/ v_minmax/maxmin_f16_fake16` in Post-GFX11, have to update the CodeGen
pattern for `v_minmax/maxmin_f16` to get CodeGen test passing.
2024-12-18 18:04:50 -05:00
Brox Chen
e10b12e656
[AMDGPU][True16][MC] true16 for v_div_fixup_f16 (#119613)
Support true16 format for v_div_fixup_f16 in MC.
2024-12-18 18:01:13 -05:00
Brox Chen
dc0ea0f945
[AMDGPU][True16][MC] true16 for v_cvt_pknorm_i16/u16_f16 (#119605)
Support true16 format for v_cvt_pknorm_i16/u16_f16 in MC.
2024-12-18 17:56:34 -05:00
Jun Wang
d57230c72e
[AMDGPU][MC] Disallow op_sel in some VOP3P dot instructions (#100485)
In v_dot4 and v_dot8 instructions with 4- or 8-bit packed data (e.g.,
v_dot4_u32_u8, v_dot8_u32_u4), the op_sel modifier should not be
allowed.
2024-12-18 10:50:47 -08:00
Brox Chen
c6f753b9a0
[AMDGPU][True16][MC] true16 for v_pack_b32_f16 (#119630)
Support true16 format for v_pack_b32_f16  in MC.

Since we are replacing v_alignbit_b32 to
`v_pack_b32_f16_t16/v_pack_b32_f16_fake16` in Post-GFX11, have to update
the CodeGen pattern for `v_pack_b32_f16_fake16 `to get CodeGen test
passing. There is no pattern modified/created, but just replacing the
`v_pack_b32_f16` with fake16 format.

Some of the true16 CodeGen test are impacted since `v_pack_b32_f16`
selection are removed in Post-GFX11 while `v_pack_b32_f16_t16` are not
yet supported. The CodeGen patch for `v_pack_b32_f16_t16` will be done
is the following patch.
2024-12-18 13:28:42 -05:00
Jay Foad
6da676ad35 [AMDGPU] Use -triple instead of -arch in MC tests 2024-12-18 12:56:49 +00:00
Brox Chen
5c5a769cc0
[AMDGPU][True16][MC] update VOP1 dasm test with latest script (#120281)
This is a NFC. Update VOP1 dasm test with latest update script
2024-12-17 20:24:06 -05:00
Brox Chen
de2acda3df
[AMDGPU][True16][MC] support more VOP3 inst in true16/fake16 format (#113603)
Support true16 and fake16 format for more VOP3 instructions in MC

This patch updates the true16 and fake16 vop_profile for the following
instructions and update the asm/dasm tests:
v_mad_u16
v_mad_i16
v_med3_f16
v_med3_i16
v_med3_u16
v_max3_f16
v_max3_i16
v_max3_u16
v_min3_f16
v_min3_i16
v_min3_u16
v_med3_num_f16
2024-12-17 13:58:01 -05:00
Brox Chen
b26f534980
[AMDGPU][True16][MC] test update for v_and/or/xor_b16 in true16 (#119489)
This is a NFC change. Update mc test for v_and/or/xor_b16 in true16
format.

MC source change was done by previous patch and automatically enabled by
t16 pesudo
2024-12-17 13:26:59 -05:00
Jay Foad
8eb12f6775
[AMDGPU] Support s_endpgm_ordered_ps_done on GFX11 (#119230)
Support assembly/disassembly of this instruction for compatibility with
SP3, even though it has no use in GFX11. It is fully removed in GFX12.
2024-12-11 11:48:36 +00:00
Brox Chen
cbed714f2a
[AMDGPU][True16][MC] test update for v_add/sub_f16 in true16 (#118926)
This is a NFC change. Update mc test for v_add/sub_f16 in true16 format.

MC source change was done by previous patch and automatically enabled by
t16 pesudo
2024-12-09 17:58:21 -05:00
Brox Chen
b9b46de03a
[AMDGPU][MC][True16] VOP3dot instruction update for true16/fake16 (#113474)
Update VOP3dot instructions with true16 and fake16 formats.

This patch includes instructions:
v_dot2_f16_f16
v_dot2_bf16_bf16
2024-12-09 16:37:59 -05:00
Jay Foad
d1cf86fe53
[AMDGPU] Add GFX12 assembler/disassembler support for v_dual_dot2acc_* (#119211)
Do for GFX12 what #118984 did for GFX11.
2024-12-09 15:12:08 +00:00
Jay Foad
f9d6d46a8e
[AMDGPU] Add assembler/disassembler support for v_dual_dot2acc_f32_bf16 (#118984)
There is still no codegen support because the corresponding 
v_dot2c_f32_bf16 instruction is not supported on GFX11.
2024-12-09 09:47:22 +00:00
Jay Foad
3f3bcac53e
[AMDGPU] New alias v_interp_p2_new_f32 (#118968)
This is for compatibility with SP3. Also add basic testing for the new
GFX11 VINTERP encoding.
2024-12-06 15:35:32 +00:00
Brox Chen
1b4cdc401a
[AMDGPU][True16][MC]update vop3 dasm test with latest script (#118686)
This is a NFC. Update dasm test for VOP3 using latest update script
2024-12-04 17:28:10 -05:00
Matt Arsenault
15676ec552
AMDGPU: Add support for V_CVT_PK_F16_F32 instruction for gfx950 (#118300)
Co-authored-by: Shilei Tian <shilei.tian@amd.com>
2024-12-02 16:04:24 -05:00
Matt Arsenault
301c8e6047
AMDGPU: Add support for v_cvt_scalef32_sr instructions (#117820)
Co-authored-by: Shilei Tian <shilei.tian@amd.com>
2024-11-26 23:20:16 -05:00
Matt Arsenault
f87cabea26
AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (#117797)
Co-authored-by: Shilei Tian <shilei.tian@amd.com>
2024-11-26 19:52:09 -05:00
Matt Arsenault
34a8bb0da3
AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (#117796)
Co-authored-by: Shilei Tian <shilei.tian@amd.com>
2024-11-26 19:48:50 -05:00
Matt Arsenault
d3c103b80e
AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (#117795)
Co-authored-by: Shilei Tian <shilei.tian@amd.com>
2024-11-26 19:41:52 -05:00