shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
525,695 Commits 1,713 Branches 298 Tags
Commit Graph

4 Commits

Author SHA1 Message Date
Luke Lau
5cd3e97362
[RISCV] Mark vmvNr.v as implicitly using vtype (#118414) 
This was pointed out in
https://github.com/llvm/llvm-project/pull/118283#issuecomment-2512895919.
We cannot move these between vtype definitions as they depend on SEW and
require vill to be clear.
 2024-12-04 15:10:57 +08:00
Alex Bradbury
8935165659
[NFCI][test] Use lit.local.cfg in test/MachineVerifier/RISCV to gate tests (#118217) 
87cc4b48c08a627f330396f941b84671c5e591d5 added `REQUIRES:
riscv64-registered-target` to the only test in this directory. It seems
better (and also reflects what we do elsewhere, including in the AMDGPU/
subdir in MachineVerifier) to gate for all files in the directory via
lit.local.cfg.
 2024-12-02 16:33:57 +00:00
Piyou Chen
87cc4b48c0 [NFC] Fix buildbot fail by add riscv64-registered-target 2024-11-24 20:54:40 -08:00
Piyou Chen
7317a6e990
[RISCV][MachineVerifier] Use RegUnit for register liveness checking (#115980) 
For the RISC-V target, V14_V15 are not subregisters of v14m4, even
though they share some registers. Currently, the MachineVerifier reports
an error when checking register liveness for segment load/store
operations.

This patch adds additional register liveness checking, using RegUnit
instead of subregisters, to prevent this error.
 2024-11-25 12:43:39 +08:00