14 Commits

Author SHA1 Message Date
Petr Kurapov
fa6f88af10
[MLIR][XeGPU] Allow some nd ops to have argument shapes mismatch for … (#120566)
…the distributed IR case.

This patch allows `nd_load` and `nd_store` to preserve the tensor
descriptor shape during distribution to SIMT. The validation now expects
the distributed instruction to retain the `sg_map` attribute and uses it
to verify the consistency.
2025-01-22 18:03:36 +01:00
Petr Kurapov
9fa55ec3d9
[MLIR][XeGPU] Add sg_map attribute to support Work Item level semanti… (#110876)
Bring back #108864
2024-10-02 13:00:10 -05:00
Chao Chen
a7b6fdaf5d
Revert "[MLIR][XeGPU] Add sg_map attribute to support Work Item level semantics" (#110871)
Reverts #108864 since it breaks compilation
2024-10-02 10:45:14 -05:00
Petr Kurapov
3ca5d8082a
[MLIR][XeGPU] Add sg_map attribute to support Work Item level semantics (#108864)
The PR adds an attribute (sg_map) describing the distribution of
computation among work items for xegpu operations to be used in lowering
passes. The map is attached to the tensor descriptor, so the constructor
and the type are updated. Tests check the custom parser & printer. The
attribute is optional now, so no other changes required.
The complete description of the attribute can be found
[here](https://github.com/intel/mlir-extensions/blob/main/docs/rfcs/XeGPU.md#xegpu-attributes-to-support-work-item-level-semantics).
2024-10-02 10:23:55 -05:00
Chao Chen
9c697b3a02
[MLIR][XeGPU] Update the type of offsets for CreateDescOp and UpdateOffsetOp (#110741)
This PR changes the type of `offsets` operand of CreateDescOp and
UpdateOffsetOp to 1D Vector of index, for convenience of users.
2024-10-02 09:18:41 -05:00
Chao Chen
8b5e841487
[MLIR][XeGPU] Updates XeGPU TensorDescAttr and Refine Gather/Scatter definition (#109675)
Bring back #109144 with fixes to VectorToXeGPU
2024-09-24 10:14:13 -05:00
Chao Chen
09e94d09fd
Revert "[MLIR][XeGPU] Updates XeGPU TensorDescAttr and Refine Gather/Scatter definition. " (#109666)
Reverts llvm/llvm-project#109144
2024-09-23 09:32:37 -05:00
Chao Chen
2162723636
[MLIR][XeGPU] Updates XeGPU TensorDescAttr and Refine Gather/Scatter definition. (#109144)
The PR makes the following refine changes to the XeGPU dialect. 
1. Separated the old `TensorDescAttr` into two independent attributes: `BlockTensorDescAttr` and `ScatterTensorDescAttr`
2. Renamed the `MemoryScopeAttr` to `MemorySpaceAttr` and updated the enumeration value for shared memory following OpenCL standard.
3. Introduced `transpose` UnitAttr to `StoreScatterOp`and `LoadGatherOp`
4. Added memory space check for `CreateNdDesc` and `CreateDesc` op, as well as valid and invalid test cases for them.
2024-09-23 09:00:26 -05:00
Chao Chen
6c783e19ef
[MLIR][XeGPU] Refine XeGPU definitions (#100763)
This PR has following changes/fixes to XeGPU definition: 
- Fix type print format for atomic_rmw
- removed 2D support for MaskType
- Update LoadNd definition
   - Add 1D TensorDesc support 
   - Replaced vnni_axis attribute with packed attribute 
- Update DPAS op definition, limiting A to 2D vector, and B to either 2D/3D vector.
2024-08-02 17:10:02 -05:00
Chao Chen
03bb10dfb3
[MLIR][XeGPU] Add dpas, atomic, and named barrier ops (#88973)
---------

Co-authored-by: Mehdi Amini <joker.eph@gmail.com>
Co-authored-by: Adam Siemieniuk <adam.siemieniuk@intel.com>
2024-04-24 14:29:11 -05:00
Chao Chen
b01879ec1f
[MLIR][XeGPU] Add XeGPU scattered ops (#86594)
- Extended TensorDescAttr with scattered attribute
- Add scattered ops: CreateDescOp, PrefetchOp, LoadGatherOp,
StoreScatterOp, UpdateOffsetOp
- Add a block op: UpdateNdOffsetOp

---------

Co-authored-by: Mehdi Amini <joker.eph@gmail.com>
Co-authored-by: Adam Siemieniuk <adam.siemieniuk@intel.com>
2024-04-16 13:44:14 -05:00
Chao Chen
61b24c61a9
[MLIR][XeGPU] Adding XeGPU 2d block operators (#85804)
This PR adds XeGPU 2D block operators. It contains:
1. TensorDescType and TensorDescAttr definitions
2. MemoryScopeAttr and CacheHintAttr definitions which are used by
TensorDescAttr.
3. CreateNdDescOp, PrefetchNdOp, LoadNdOp, and StoreNdOp definitions,
and their corresponding testcases for illustration.

It cherry-picks daebe5c4f27ba140ac8d13abf41e3fe4db72b91a with asan fix.

---------

Co-authored-by: Mehdi Amini <joker.eph@gmail.com>
2024-03-20 17:32:30 -05:00
Balaji V. Iyer
8d142043e8
Revert "[MLIR][XeGPU] Adding XeGPU 2d block operators (#84692)" (#85653)
This reverts commit daebe5c4f27ba140ac8d13abf41e3fe4db72b91a.

This commit causes the following asan issue:

```
<snip>/llvm-project/build/bin/mlir-opt <snip>/llvm-project/mlir/test/Dialect/XeGPU/XeGPUOps.mlir | <snip>/llvm-project/build/bin/FileCheck <snip>/llvm-project/mlir/test/Dialect/XeGPU/XeGPUOps.mlir
# executed command: <snip>/llvm-project/build/bin/mlir-opt <snip>/llvm-project/mlir/test/Dialect/XeGPU/XeGPUOps.mlir
# .---command stderr------------
# | =================================================================
# | ==2772558==ERROR: AddressSanitizer: stack-use-after-return on address 0x7fd2c2c42b90 at pc 0x55e406d54614 bp 0x7ffc810e4070 sp 0x7ffc810e4068
# | READ of size 8 at 0x7fd2c2c42b90 thread T0
# |     #0 0x55e406d54613 in operator()<long int const*> /usr/include/c++/13/bits/predefined_ops.h:318
# |     #1 0x55e406d54613 in __count_if<long int const*, __gnu_cxx::__ops::_Iter_pred<mlir::verifyListOfOperandsOrIntegers(Operation*, llvm::StringRef, unsigned int, llvm::ArrayRef<long int>, ValueRange)::<lambda(int64_t)> > > /usr/include/c++/13/bits/stl_algobase.h:2125
# |     #2 0x55e406d54613 in count_if<long int const*, mlir::verifyListOfOperandsOrIntegers(Operation*, 
...
```
2024-03-18 11:27:58 -05:00
Chao Chen
daebe5c4f2
[MLIR][XeGPU] Adding XeGPU 2d block operators (#84692)
Hi @joker-eph, This PR adds XeGPU 2D block operators. It contains:
1. `TensorDescType` and `TensorDescAttr` definitions
2. `MemoryScopeAttr` and `CacheHintAttr` definitions which are used by
`TensorDescAttr`.
3. `CreateNdDescOp`, `PrefetchNdOp`, `LoadNdOp`, and `StoreNdOp`
definitions, and their corresponding testcases for illustration.

---------

Co-authored-by: Mehdi Amini <joker.eph@gmail.com>
2024-03-18 07:09:47 -05:00