10910 Commits

Author SHA1 Message Date
Krzysztof Drewniak
92a15dd748
[mlir][LLVM] Plumb range attributes on parameters and results through (#117801)
We've had the ability to define LLVM's `range` attribute through
 #llvm.constant_range for some time, and have used this for some GPU
intrinsics. This commit allows using `llvm.range` as a parameter or
result attribute on function declarations and definitions.
2024-11-27 12:31:51 -06:00
Victor Perez
a807bbea6f
[MLIR][GPUToLLVMSPV] Use llvm.func attributes to convert gpu.shuffle (#116967)
Use `llvm.func`'s `intel_reqd_sub_group_size` attribute instead of
SPIR-V environment attributes in the `gpu.shuffle` conversion pattern.
This metadata is needed to check the semantics of the operation are
supported, i.e., it has a constant width and its value is equal to the
sub-group size.

As the pass also converts `gpu.func` to `llvm.func`, adding a
discardable attribute of name `intel_reqd_sub_group_size` attribute to
the latter is enough for this pattern to work.

We no longer have a notion of "default" sub-group size, so this
attribute needs to be set in the parent function for `gpu.shuffle`
operations to be converted.

Drop dependency on the SPIR-V dialect as we no longer require creating
attributes from this dialect to lower `gpu.shuffle` instances.

---------

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2024-11-27 15:04:38 +01:00
Matthias Springer
2ff2e871f5
[mlir][bufferization] Remove remaining dialect conversion-based infra parts (#114155)
This commit removes the last remaining components of the dialect
conversion-based bufferization passes.

Note for LLVM integration: If you depend on these components, migrate to
One-Shot Bufferize or copy them to your codebase.
2024-11-27 09:54:22 +09:00
Ian Wood
06514c5501
[MLIR][Linalg] Fix linalg crash during elementwise op fusion (#117667)
`isOpOperandCanBeDroppedAfterFusedLinalgs` crashes when `indexingMaps`
is empty. This can occur when `producer` only has DPS init operands and
`consumer ` only has a single DPS input operand (all operands are
ignored and nothing gets added to `indexingMaps`). This is because
`concatAffineMaps` wasn't handling the maps being empty properly.


Similar to `canOpOperandsBeDroppedImpl`, I added an early return when
the maps are of size zero. Additionally, `concatAffineMaps`'s
declaration comment says it returns an empty map when `maps` is empty
but it has no way to get the `MLIRContext` needed to construct the empty
affine map when the array is empty. So, I changed this to take the
context.


__NOTE: concatAffineMaps now takes an MLIRContext to be able to
construct an empty map in the case where `maps` is empty.__

---------

Signed-off-by: Ian Wood <ianwood2024@u.northwestern.edu>
Co-authored-by: Quinn Dawkins <quinn.dawkins@gmail.com>
2024-11-26 16:00:18 -08:00
Christopher Bate
ced2fc7819
[mlir][bufferization] Fix OneShotBufferize when defaultMemorySpaceFn is used (#91524)
As described in issue llvm/llvm-project#91518, a previous PR
llvm/llvm-project#78484 introduced the `defaultMemorySpaceFn` into
bufferization options, allowing one to inform OneShotBufferize that it
should use a specified function to derive the memory space attribute
from the encoding attribute attached to tensor types.

However, introducing this feature exposed unhandled edge cases,
examples of which are introduced by this change in the new test under

`test/Dialect/Bufferization/Transforms/one-shot-bufferize-encodings.mlir`.

Fixing the inconsistencies introduced by `defaultMemorySpaceFn` is
pretty simple. This change:

- Updates the `bufferization.to_memref` and `bufferization.to_tensor`
  operations to explicitly include operand and destination types,
  whereas previously they relied on type inference to deduce the
  tensor types. Since the type inference cannot recover the correct
  tensor encoding/memory space, the operand and result types must be
  explicitly included. This is a small assembly format change, but it
  touches a large number of test files.

- Makes minor updates to other bufferization functions to handle the
  changes in building the above ops.

- Updates bufferization of `tensor.from_elements` to handle memory
  space.


Integration/upgrade guide:

In downstream projects, if you have tests or MLIR files that explicitly
use
`bufferization.to_tensor` or `bufferization.to_memref`, then update
them to the new assembly format as follows:

```
%1 = bufferization.to_memref %0 : memref<10xf32>
%2 = bufferization.to_tensor %1 : memref<10xf32>
```

becomes

```
%1 = bufferization.to_memref %0 : tensor<10xf32> to memref<10xf32>
%2 = bufferization.to_tensor %0 : memref<10xf32> to tensor<10xf32> 
```
2024-11-26 09:45:57 -07:00
Andrzej Warzyński
b214ca82da
[mlir][vector] Rename vector type TD definitions (nfc) (#117150)
Currently, the Vector dialect TD file includes the following "vector"
type definitions:

```mlir
def AnyVector : VectorOf<[AnyType]>;
def AnyVectorOfAnyRank : VectorOfAnyRankOf<[AnyType]>;
def AnyFixedVector : FixedVectorOf<[AnyType]>;
def AnyScalableVector : ScalableVectorOf<[AnyType]>;
```

In short:

  * `AnyVector` _excludes_ 0-D vectors.
  * `AnyVectorOfAnyRank`, `AnyFixedVector`, and `AnyScalableVector`
    _include_ 0-D vectors.

The naming for "groups" that include 0-D vectors is inconsistent and can
be misleading, and `AnyVector` implies that 0-D vectors are included,
which is not the case.

This patch renames these definitions for clarity:

```mlir
def AnyVectorOfNonZeroRank : VectorOfNonZeroRankOf<[AnyType]>;
def AnyVectorOfAnyRank : VectorOfAnyRankOf<[AnyType]>;
def AnyFixedVectorOfAnyRank : FixedVectorOfAnyRank<[AnyType]>;
def AnyScalableVectorOfAnyRank : ScalableVectorOfAnyRank<[AnyType]>;
```

Rationale:
* The updated names are more explicit about 0-D vector support.
* It becomes clearer that scalable vectors currently allow 0-D vectors -
  this might warrant a revisit.
* The renaming paves the way for adding a new group for "fixed-width
  vectors excluding 0-D vectors" (e.g., AnyFixedVector), which I plan to
  introduce in a follow-up patch.
2024-11-26 14:59:39 +00:00
Victor Perez
59b3630e03
[MLIR][SPIR-V] Drop commas from split barrier operations ASM format (#116673)
Drop commas from split barrier operations assembly format.

Signed-off-by: Victor Perez <victor.perez@codeplay.com>


Depends on #116648, review ec8d35471602cd88aa2ebaf239b698ef3ba353bd
only.

---------

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2024-11-26 15:08:31 +01:00
lorenzo chelini
4a7b56e6e7
[MLIR][Arith] Add denormal attribute to binary/unary operations (#112700)
Add support for denormal in the Arith dialect (binary and unary
operations).
Denormal are attached to every operation, and they can be of three
different
kinds:

1) ieee, denormal are preserved and processed as defined by IEEE 754
rules.

2) preserve sign, a mode where denormal numbers are flushed to zero, but
the
sign of the zero (+0 or -0) is preserved.

3) positive zero, a mode where all denormal numbers are flushed to
positive zero
(+0), ignoring the sign of the original number.

Denormal refers to both the operands and the result. Currently only
lowering for
ieee is supported.
2024-11-26 11:58:43 +01:00
Andrzej Warzyński
1b2c8f104f
[mlir][linalg] Extract GeneralizePadOpPattern into a standalone transformation (#117329)
Currently, `GeneralizePadOpPattern` is grouped under
`populatePadOpVectorizationPatterns`. However, as noted in #111349, this
transformation "decomposes" rather than "vectorizes" `tensor.pad`. As
such, it functions as:
  * a vectorization _pre-processing_ transformation, not
  * a vectorization transformation itself.

To clarify its purpose, this PR turns `GeneralizePadOpPattern` into a
standalone transformation by:
  * introducing a dedicated `populateDecomposePadPatterns` method,
  * adding a `apply_patterns.linalg.decompose_pad` Transform Dialect Op,
  * removing it from `populatePadOpVectorizationPatterns`.

In addition, to better reflect its role, it is renamed as "decomposition"
rather then "generalization".  This is in line with the recent renaming
of similar ops, i.e. tensor.pack/tensor.unpack Ops in #116439.
2024-11-26 08:11:15 +00:00
ddubov100
7e3187e12a
Adding mlir prefix for missing places in TilingInterface.td (#117495) 2024-11-25 17:33:43 +02:00
Yadong Chen
a5506a39e0
[mlir][spirv] Use assemblyFormat to define {InBound}PtrAccessChainOp assembly (#116943)
Declarative assemblyFormat ODS is more concise and requires less
boilerplate than filling out cpp interfaces.

Changes:
updates the PtrAccessChainOp and InBoundPtrAccessChainOp defined in
SPIRVMemoryOps.td to use assemblyFormat. Removes part print/parse from
MemoryOps.cpp which is now generated by assemblyFormat
Updates tests to updated format

Issue: #73359
2024-11-25 10:11:07 -05:00
Markus Böck
d35098bfa8
[mlir][LLVM][NFC] Move LLVMStructType to ODS (#117485)
This PR extracts NFC changes out of
https://github.com/llvm/llvm-project/pull/116035 to reap as many of the
same benefits without any of the semantic changes.

More concretely, moving `LLVMStructType` to ODS has the benefits of
being able to generate much of the required boilerplate, such as
interface definitions, documentation and more, automatically.
Furthermore, `LLVMStructType` is then treated less special and its
definition can be found at the same place where all other complex type
definitions are found in the LLVM dialect.

Future changes could leverage more automatically generated code from
TableGen such as `assemblyFormat`. As these are not as trivial, they
have been left for future PRs.

---------

Co-authored-by: Tobias Gysi <tobias.gysi@nextsilicon.com>
2024-11-25 10:02:53 +01:00
Fabian Mora
7498eaa9ab
[mlir][LLVM] Add the ConvertToLLVMAttrInterface and ConvertToLLVMOpInterface interfaces (#99566)
This patch adds the `ConvertToLLVMAttrInterface` and
`ConvertToLLVMOpInterface` interfaces. It also modifies the
`convert-to-llvm` pass to use these interfaces when available.

The `ConvertToLLVMAttrInterface` interfaces allows attributes to
configure conversion to LLVM, including the conversion target, LLVM type
converter, and populating conversion patterns. See the `NVVMTargetAttr`
implementation of this interface for an example of how this interface
can be used to configure conversion to LLVM.

The `ConvertToLLVMOpInterface` interface collects all convert to LLVM
attributes stored in an operation.

Finally, the `convert-to-llvm` pass was modified to use these interfaces
when available. This allows applying `convert-to-llvm` to GPU modules
and letting the `NVVMTargetAttr` decide which patterns to populate.
2024-11-24 10:09:43 -05:00
Mehdi Amini
c8b837ad8c
[MLIR][Python] Add the --mlir-print-ir-tree-dir to the C and Python API (#117339) 2024-11-23 20:17:25 +01:00
Jacques Pienaar
01e75646a5
[mlir] Add FileRange location type. (#80213)
This location type represents a contiguous range inside a file. It is
effectively a pair of FileLineCols. Add new type and make FileLineCol a
view for case where it matches existing previous one.

The location includes filename and optional start line & col, and end
line & col. Considered common cases are file:line, file:line:col,
file:line:start_col to file:line:end_col and general range within same
file. In memory its encoded as trailing objects. This keeps the memory
requirement the same as FileLineColLoc today (makes the rather common
File:Line cheaper) at the expense of extra work at decoding time. Kept the unsigned
type.

There was the option to always have file range be castable to
FileLineColLoc. This cast would just drop other fields. That may result
in some simpler staging. TBD.

This is a rather minimal change, it does not yet add bindings (C or
Python), lowering to LLVM debug locations etc. that supports end line:cols.

---------

Co-authored-by: River Riddle <riddleriver@gmail.com>
2024-11-23 05:12:04 -08:00
Petr Kurapov
ecaf2c335c
[MLIR] Move warp_execute_on_lane_0 from vector to gpu (#116994)
Please see the related RFC here:
https://discourse.llvm.org/t/rfc-move-execute-on-lane-0-from-vector-to-gpu-dialect/82989.

This patch does exactly one thing - moves the op to gpu.
2024-11-22 15:30:47 +01:00
Mikhail Goncharov
562c93a165 [mlir] IWYU mlir/include/mlir/Query/QuerySession.h 2024-11-22 09:16:04 +01:00
Uday Bondhugula
454398ab04
[MLIR] Add missing memory read effect on memref.reshape (#117130)
The memory read effect on a memref.reshape argument was missing. This in
turn led to
analyses relying on memory effects making incorrect conclusions.
2024-11-22 07:54:54 +05:30
Krzysztof Drewniak
9e8200c718
[mlir][Affine] Expand affine.[de]linearize_index without affine maps (#116703)
As the documentation for -affine-expand-index-ops says,
affine.delinearize_index and affine.linearize_index don't need to be
expanded into the affine dialect.

Expanding these operations into affine.apply operations can introduce
unwanted "simplifications", mainly translations of `(dN mod C + ...)` to
`(dN + ... - (dN floordiv C) * C)` and similar, which create worse
generated code. This commit resolves this issue by expanding out
affine.delanierize_index directly.

In addition, the lowering of affine.linearize_index now sorts the
operands by loop-independence, allowing an increased amount of
loop-invariant code motion after lowering.

The old behavior is preserved as -expand-affine-index-ops-as-affine but
is no longer the default
2024-11-21 11:36:32 -06:00
Christopher McGirr
e8b5c009b6
[mlir][spirv]: Add Broadcom Vendor (#116600)
This PR is simply adding the Broadcom vendor ID to the SPIRV list. In
order to enable the use of this vendor ID in a SPIRV pipeline for the
Videocore GPUs.
2024-11-21 10:11:49 -05:00
Diego Caballero
32913724ac
[mlir][vector] Fix 0-d vector transfer mask inference (#116526)
When inferring the mask of a transfer operation that results in a single `i1` element, 
we could represent it using either `vector<i1>` or vector<1xi1>. To avoid type mismatches,
this PR updates the mask inference logic to consistently generate `vector<1xi1>` for
these cases. We can enable 0-D masks if they are needed in the future.

See: https://github.com/llvm/llvm-project/issues/116197
2024-11-20 20:57:39 -08:00
Matthias Springer
cbc7802233
[mlir][bufferization] Remove finalizing-bufferize pass (#114154)
The dialect conversion-based bufferization passes have been migrated to
One-Shot Bufferize about two years ago. To clean up the code base, this
commit removes the `finalizing-bufferize` pass, one of the few remaining
parts of the old infrastructure. Most bufferization passes have already
been removed.

Note for LLVM integration: If you depend on this pass, migrate to
One-Shot Bufferize or copy the pass to your codebase.

Depends on #114152.
2024-11-21 10:51:23 +09:00
arthurqiu
81055ff070
[mlir][nvvm] Add attributes for cluster dimension PTX directives (#116973)
PTX programming models provides cluster dimension directives, which are
leveraged by the downstream `ptxas` compiler. See
https://docs.nvidia.com/cuda/nvvm-ir-spec/#supported-properties and
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#cluster-dimension-directives

This PR introduces the cluster dimension directives to MLIR's NVVM
dialect as listed below:
```
cluster_dim_{x,y,z}    ->    exact number of CTAs per cluster
cluster_max_blocks     ->    max number of CTAs per cluster
```
2024-11-20 18:31:01 +01:00
Zichen Lu
08e7609692
[mlir][fix] Add callback functions for ModuleToObject (#116916)
Here is the [merged
MR](https://github.com/llvm/llvm-project/pull/116007) which caused a
failure and [was
reverted](https://github.com/llvm/llvm-project/pull/116811).

Thanks to @joker-eph for the help, I fix it (miss constructing
`ModuleObject` with callback functions in
`mlir/lib/Target/LLVM/NVVM/Target.cpp`) and split unit tests from origin
test which don't need `ptxas` to make the test runs more widely.
2024-11-20 13:22:08 +01:00
Md Asghar Ahmad Shahid
288f05f63e
[NFC][MLIR][Linalg] Refactor linalg.matmul tablegen ODS and related C++ code. (#116377)
This commit refactors part of the code in preparation for the migration
of other *matmul* variants from OpDSL to ODS.
Moves getDefaultIndexingmaps() helper into the MatmulOp class.
2024-11-20 09:26:06 +00:00
Matthias Springer
e394fecd5b
[mlir][func] Remove func-bufferize pass (#114152)
The dialect conversion-based bufferization passes have been migrated to
One-Shot Bufferize about two years ago. To clean up the code base, this
commit removes the `func-bufferize` pass, one of the few remaining parts
of the old infrastructure. Most bufferization passes have already been
removed.

Note for LLVM integration: If you depend on this pass, migrate to
One-Shot Bufferize or copy the pass to your codebase.
2024-11-20 09:29:26 +09:00
Perry Gibson
21df32511b
[mlir,python] Expose replaceAllUsesExcept to Python bindings (#115850)
Problem originally described in [the forums
here](https://discourse.llvm.org/t/mlir-python-expose-replaceallusesexcept/83068/1).

Using the MLIR Python bindings, the method
[`replaceAllUsesWith`](https://mlir.llvm.org/doxygen/classmlir_1_1Value.html#ac56b0fdb6246bcf7fa1805ba0eb71aa2)
for `Value` is exposed, e.g.,

```python
orig_value.replace_all_uses_with(
    new_value               
)
```

However, in my use-case I am separating a block into multiple blocks, so
thus want to exclude certain Operations from having their Values
replaced (since I want them to diverge).

Within Value, we have
[`replaceAllUsesExcept`](https://mlir.llvm.org/doxygen/classmlir_1_1Value.html#a9ec8d5c61f8a6aada4062f609372cce4),
where we can pass the Operations which should be skipped.

This is not currently exposed in the Python bindings: this PR fixes
this. Adds `replace_all_uses_except`, which works with individual
Operations, and lists of Operations.
2024-11-19 19:00:57 -05:00
Kyle Wang
d8bd7f11c8
[mlir] Support ROCDL::ReadlaneOp (#116593)
Support ROCDL::ReadlaneOp to solve
https://github.com/ROCm/triton-internal/issues/411.
2024-11-19 17:36:30 -06:00
Md Abdullah Shahneous Bari
27046bad97
[mlir][XeGPU] Add a builder for xegpu.create_nd_tdesc op. (#116472)
The builder is needed to support dynamic meref as source operand in
xegpu.create_nd_tdesc op.
2024-11-19 15:15:53 -06:00
ddubov100
68b7ab127f
[MLIR] Fully qualify entities in the ::mlir namespace in TilingInterface.td. (#116765)
Adding mlir namespace to TilingInterface.td. 
Otherwise it can't be used with dialects not nested under the mlir
namespace.
2024-11-19 20:16:35 +01:00
Mehdi Amini
af41c55673
Revert "[MLIR] Add callback functions for ModuleToObject" (#116811)
Reverts llvm/llvm-project#116007

Bot is broken.
2024-11-19 15:28:17 +01:00
Yadong Chen
bdf00e2216
[mlir][spirv] Use assemblyFormat to define AccessChainOp assembly (#116545)
see #73359

Declarative assemblyFormat ODS is more concise and requires less
boilerplate than filling out cpp interfaces.

Changes:
- updates the AccessChainOp defined in SPIRVMemoryOps.td to use
assemblyFormat.
- Removes part print/parse from MemoryOps.cpp which is now generated by
assemblyFormat
- Updates tests to updated format
2024-11-19 09:15:52 -05:00
Zichen Lu
2153672ba3
[MLIR] Add callback functions for ModuleToObject (#116007)
In ModuleToObject flow, users may want to add some callback functions
invoked with LLVM IR/ISA for debugging or other purposes.
2024-11-19 13:51:08 +01:00
Andrzej Warzyński
0775088234
[mlir] Rename GeneralizeOuterUnitDims{Un}PackOpPatterns (#116439)
Renames:
  * `GeneralizeOuterUnitDimsPackOpPattern`,
  * `GeneralizeOuterUnitDimsUnPackOpPattern`,

as
  * `DecomposeOuterUnitDimsPackOpPattern`,
  * `DecomposeOuterUnitDimsUnPackOpPattern`,

respectively. The new name better describes the underlying
transformation.
2024-11-19 09:09:33 +00:00
Ivan R. Ivanov
980d5fb2d0
[MLIR][omp] Add omp operations for OpenMP workshare (#101443)
Add the `omp.workshare` and `omp.workshare.loop_wrapper` operations used for the implementation of the `workshare` construct in flang.
2024-11-19 16:43:05 +09:00
Krzysztof Drewniak
31aa7f34e0
[mlir][Affine] Let affine.[de]linearize_index omit outer bounds (#116103)
The affine.delinearize_index and affine.linearize_index operations, as
currently defined, require providing a length N basis to [de]linearize N
values. The first value in this basis is never used during lowering and
is unused during lowering. (Note that, even though it isn't used during
lowering it can still be used to, for example, remove length-1 outputs
from a delinearize).

This dead value makes sense in the original context of these operations,
which is linearizing or de-linearizing indexes to memref<>s, vector<>s,
and other shaped types, where that outer bound is avaliable and may be
useful for analysis.

However, other usecases exist where the outer bound is not known. For
example:

    %thread_id_x = gpu.thread_id x : index
%0:3 = affine.delinearize_index %thread_id_x into (4, 16) : index,index,
index

In this code, we don't know the upper bound of the thread ID, but we do
want to construct the ?x4x16 grid of delinearized values in order to
further partition the GPU threads.

In order to support such usecases, we broaden the definition of
affine.delinearize_index and affine.linearize_index to make the outer
bound optional.

In the case of affine.delinearize_index, where the number of results is
a function of the size of the passed-in basis, we augment all existing
builders with a `hasOuterBound` argument, which, for backwards
compatibilty and to preserve the natural usage of the op, defaults to
`true`. If this flag is true, the op returns one result per basis
element, if it is false, it returns one extra result in position 0.

We also update existing canonicalization patterns (and move one of them
into the folder) to handle these cases. Note that disagreements about
the outer bound now no longer prevent delinearize/linearize
cancelations.
2024-11-18 15:41:54 -06:00
Matthias Gehre
68a3908148
emitc: func: Set default dialect to 'emitc' (#116297)
Makes `emitc.func` implement the `OpAsmOpInterface` and overwrite the
`getDefaultDialect`. This allows ops inside `emitc.func`'s body to omit
the 'emitc.' prefix in the assembly.
2024-11-18 17:26:21 +01:00
Victor Perez
ad3b291879
[MLIR][SPIRV] Add definition for SPV_INTEL_split_barrier ops (#115738)
The [`SPV_INTEL_split_barrier`  extension](https://htmlpreview.github.io/?https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_split_barrier.html)
defines operations to split control barrier semantics in two operations.
Add support for these operations (arrive and wait) to the dialect.

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2024-11-18 12:08:54 +01:00
sondre-teigen
37feced61e
[mlir][Tosa] Fix typo in avg_pool2d summary (#116538) 2024-11-18 10:13:58 +00:00
Victor Perez
4f78f85190
[MLIR][SPIRV] Add definition and (de)serialization for cache controls (#115461)
[SPV_INTEL_cache_controls](https://htmlpreview.github.io/?https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_cache_controls.html)
defines decorations for load and store cache control. Add support for
this extension in the SPIR-V dialect.

As several `CacheControlLoadINTEL` and `CacheControlStoreINTEL` may be
applied to the same value, these are represented as array attributes.
(De)Serialization takes care of this representation.

---------

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2024-11-18 09:42:31 +01:00
Andrzej Warzyński
63b926af5f
[mlir] Add apply_patterns.linalg.generalize_pack_unpack TD Op (#116373)
This PR introduces populateGeneralizePatterns, which collects the
following patterns:

  * `GeneralizeOuterUnitDimsPackOpPattern`,
  * `GeneralizeOuterUnitDimsUnPackOpPattern` (currently a TODO).

These patterns are wrapped in a new Transform Dialect Op:
`apply_patterns.linalg.generalize_pack_unpack`. This Op facilitates
creating more involved end-to-end compilation pipelines for
`tensor.pack` and `tensor.unpack` operations. It will be required in an
upcoming PR building on top of #115698.

No new tests are added in this PR. Instead, existing tests from:

  * "generalize-tensor-pack.mlir"

are reused. To achieve this:

  * I've updated the test to use
    `transform.apply_patterns.linalg.generalize_pack_unpack` instead of
    the flag
    `--test-linalg-transform-patterns="test-generalize-tensor-pack"`,
    avoiding artificial tests solely for the TD Op.
  * The TD sequence is saved to a new file, "generalize_pack.mlir", and
    pre-loaded using the option:

`--transform-preload-library='transform-library-paths=%p/td/generalize_pack.mlir'`
    This avoids duplicating the sequence for every "split" in the input
    file.
  * Added "lit.local.cfg" to exclude the "test/Dialect/Linalg/td"
    directory from test discovery, ensuring "generalize_pack.mlir" is
    not treated as a test file.
2024-11-18 07:51:18 +00:00
Kareem Ergawy
fd3ff2007a
[flang][OpenMP] Add basic support to lower loop directive to MLIR (#114199)
Adds initial support for lowering the `loop` directive to MLIR.

The PR includes basic suport and testing for the following clauses:
 * `collapse`
 * `order`
 * `private`
 * `reduction`

Parent PR: #113911, only the latest commit is relevant to this PR.
2024-11-18 06:23:27 +01:00
agozillon
b5db75bfce
[OpenMP][MLIR] Descriptor explicit member map lowering changes (#113556)
This is one of 3 PRs in a PR stack that aims to add support for explicit
mapping of allocatable members in derived types.

The primary changes in this PR are the OpenMPToLLVMIRTranslation.cpp
changes, which are small and seek to alter the current member mapping to
add an additional map insertion for pointers. Effectively, if the member
is a pointer (currently indicated by having a varPtrPtr field) we add an
additional map for the pointer and then alter the subsequent mapping of
the member (the data) to utilise the member rather than the parents base
pointer. This appears to be necessary in certain cases when mapping
pointer data within record types to avoid segfaulting on device (due to
incorrect data mapping). In general this record type mapping may be
simplifiable in the future.

There are also additions of tests which should help to showcase the
affect of the changes above.
2024-11-16 12:26:29 +01:00
Kunwar Grover
db115ba3ef
[mlir][Linalg] Fix non-matmul linalg structured ops (#116412)
3ad0148020
broke linalg structured ops other than MatmulOp.

The patch:

- Changes the printer to hide additional attributes, which weren't
hidden before: "indexing_maps".
- Changes the build of every linalg structured op to have an indexing
map for matmul.

These changes combined, hide the problem until you print the operation
in it's generic form.

Reproducer:

```mlir
func.func public @bug(%arg0 : tensor<5x10x20xf32>, %arg1 : tensor<5x20x40xf32>, %arg3 : tensor<5x10x40xf32>) -> tensor<5x10x40xf32> {
  %out = linalg.batch_matmul ins(%arg0, %arg1 : tensor<5x10x20xf32>, tensor<5x20x40xf32>)
      outs(%arg3 : tensor<5x10x40xf32>) -> tensor<5x10x40xf32>
  func.return %out : tensor<5x10x40xf32>
}
```

Prints fine, with `mlir-opt <file>`, but if you do `mlir-opt
--mlir-print-op-generic <file>`:

```
#map = affine_map<(d0, d1, d2) -> (d0, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#map3 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
#map4 = affine_map<(d0, d1, d2, d3) -> (d0, d3, d2)>
#map5 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2)>
"builtin.module"() ({
  "func.func"() <{function_type = (tensor<5x10x20xf32>, tensor<5x20x40xf32>, tensor<5x10x40xf32>) -> tensor<5x10x40xf32>, sym_name = "bug", sym_visibility = "public"}> ({
  ^bb0(%arg0: tensor<5x10x20xf32>, %arg1: tensor<5x20x40xf32>, %arg2: tensor<5x10x40xf32>):
    %0 = "linalg.batch_matmul"(%arg0, %arg1, %arg2) <{operandSegmentSizes = array<i32: 2, 1>}> ({
    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
      %1 = "arith.mulf"(%arg3, %arg4) <{fastmath = #arith.fastmath<none>}> : (f32, f32) -> f32
      %2 = "arith.addf"(%arg5, %1) <{fastmath = #arith.fastmath<none>}> : (f32, f32) -> f32
      "linalg.yield"(%2) : (f32) -> ()
    }) {indexing_maps = [#map, #map1, #map2], linalg.memoized_indexing_maps = [#map3, #map4, #map5]} : (tensor<5x10x20xf32>, tensor<5x20x40xf32>, tensor<5x10x40xf32>) -> tensor<5x10x40xf32>
    "func.return"(%0) : (tensor<5x10x40xf32>) -> ()
  }) : () -> ()
}) : () -> ()
```

The batch_matmul operation's builder now always inserts a indexing_map
which is unrelated to the operation itself. This was caught when a
transformation from one LinalgStructuredOp to another, tried to pass
it's attributes to the other ops builder and there were multiple
indexing_map attributes in the result.

This patch fixes this by specializing the builders for MatmulOp with
indexing map information.
2024-11-16 08:13:10 +00:00
lfrenot
40afff7bd9
[mlir][LLVM] Add disjoint flag (#115855)
The implementation is mostly based on the one existing for the exact
flag.

disjoint means that for each bit, that bit is zero in at least one of
the inputs. This allows the Or to be treated as an Add since no carry
can occur from any bit. If the disjoint keyword is present, the result
value of the or is a [poison
value](https://llvm.org/docs/LangRef.html#poisonvalues) if both inputs
have a one in the same bit position. For vectors, only the element
containing the bit is poison.
2024-11-15 13:48:01 +01:00
Durgadoss R
1b23ebe077
[MLIR][NVVM] Add Op for TMA Prefetch (#116232)
PR #115527 adds intrinsics for TMA prefetch.
This patch adds an NVVM Dialect Op for the same.

Lit tests to verify the lowering to LLVM intrinsics as well as
verifier tests (for invalid cases) are added.

PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-prefetch-tensor

Signed-off-by: Durgadoss R <durgadossr@nvidia.com>
2024-11-15 11:22:48 +05:30
Jinyun (Joey) Ye
618f231a6d
[MLIR][Transform] Consolidate result of structured.split into one list (#111171)
Follow-up a review comment from
https://github.com/llvm/llvm-project/pull/82792#discussion_r1604925239
as a separate PR:

	E.g.:
	```
	%0:2 = transform.structured.split
	```
	is changed to
	```
	%t = transform.structured.split
	%0:2 = transform.split_handle %t
	```
2024-11-15 10:53:34 +08:00
Thomas Peters
aa81c28cd5
[MLIR][mlir-opt] Add option to turn off verifier on parsing (#116287)
Sometimes, a developer may not wish to wait for the verifier
(imagine they did not follow the verifier guidelines and chased use-def
chains), or may wish to disable it.

Add a command-line option,
`--mlir-very-unsafe-disable-verifier-on-parsing`, which turns off the
verifier on parsing.

------

This implements the discussion from
https://discourse.llvm.org/t/optionally-turn-off-verifier-during-parsing/82805
2024-11-15 00:23:45 +01:00
Markus Böck
402efa733c
[mlir][LLVM] Remove redundant custom<LLVMOpAttrs> (#116207)
This custom printer was previously used to avoid printing fast math
flags if they have default values.

This is redundant however, as `attr-dict` will already elide attributes
whose default values are set, making it a noop nowadays.
2024-11-14 13:34:31 +01:00
Abdul Raheem
8ff2da782d
[MLIR][NFC] Fix comment formatting and use 3 slashes (#116201)
NFC making a consistent indentation.
Corrected comment syntax. Changed // to ///
and nit grammatical change.
2024-11-14 12:24:32 +01:00