llvm-project

shylie/llvm-project

Fork 0

Commit Graph

Author	SHA1	Message	Date
Hsiangkai Wang	c7189ba785	[RISCV] Add new vector instructions in v0.10. * Add new vector instructions in v0.10. - load/store for mask value vle1.v vse1.v - vsetivli for 0-31 immediate vector length. * Rename vector instructions in v0.10. - vfrsqrte7 -> vfrsqrt7 - vfrece7 -> vfrec7 * Reserve memory width encodings for EEW>128b. Differential Revision: https://reviews.llvm.org/D95781	2021-02-03 13:28:58 +08:00
Craig Topper	b577d2df7b	[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block. Add simple pass for removing redundant vsetvli instructions within a basic block. This handles the case where the AVL register and VTYPE immediate are the same and no other instructions that change VTYPE or VL are between them. There are going to be more opportunities for improvement in this space as we development more complex tests. Differential Revision: https://reviews.llvm.org/D92679	2020-12-11 10:35:37 -08:00

Author

SHA1

Message

Date

Hsiangkai Wang

c7189ba785

[RISCV] Add new vector instructions in v0.10.

* Add new vector instructions in v0.10.
 - load/store for mask value vle1.v vse1.v
 - vsetivli for 0-31 immediate vector length.
* Rename vector instructions in v0.10.
 - vfrsqrte7 -> vfrsqrt7
 - vfrece7 -> vfrec7
* Reserve memory width encodings for EEW>128b.

Differential Revision: https://reviews.llvm.org/D95781

2021-02-03 13:28:58 +08:00

Craig Topper

b577d2df7b

[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.

Add simple pass for removing redundant vsetvli instructions within a basic block. This handles the case where the AVL register and VTYPE immediate are the same and no other instructions that change VTYPE or VL are between them.

There are going to be more opportunities for improvement in this space as we development more complex tests.

Differential Revision: https://reviews.llvm.org/D92679

2020-12-11 10:35:37 -08:00

2 Commits