519 Commits

Author SHA1 Message Date
jwanggit86
37b538819b
[AMDGPU] Incorrect error message regarding SCC modifier (#65660)
For the AMD GFX90A GPU, the SCC instruction modifier is allowed for
certain classes of instructions. However, the current assembler
generates an error message, "scc is not supported on this GPU",
regardless of the instruciton. This fix modifies the message as well as
the logic for generating the message. Related tests are moved from
gfx90a_err.s to gfx90a_asm_features.s.

Co-authored-by: Jun Wang <jun.wang7@amd.com>
2023-09-08 13:07:06 -07:00
Sergei Barannikov
a479be0f39 [MC] Change tryParseRegister to return ParseStatus (NFC)
This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variables to just Reg
(a leftover from the days when RegNo had 'unsigned' type).
2023-09-06 10:28:12 +03:00
Stanislav Mekhanoshin
cfe9a134bb [AMDGPU] Rename 64BitDPP feature and fix the checks
Names '64BitDPP' and especially 'DPP64' were found misleading, and
DPP64 can easily be mixed with DPP16 and DPP8 while these are
different concepts. DPP16 and DPP8 refers to lanes where DPP64
refers to the operand size.

In fact the essential part here is that these instructions are
executed on the DP ALU, so rename the feature accordingly.

I have also found a bug in a check for these instructions, which is
fixed here and a common utility function is now used.

Differential Revision: https://reviews.llvm.org/D158465
2023-08-22 11:00:10 -07:00
Jay Foad
18919ee759 [AMDGPU] Validate GDS in the assembler
GFX90A DS instructions cannot use the gds modifier, except for the
DS_GWS_* instructions where it is still mandatory.

Differential Revision: https://reviews.llvm.org/D157100
2023-08-11 09:21:55 +01:00
Ivan Kosarev
6b693f5e34 [AMDGPU][AsmParser][NFC] Translate parsed DS instructions to MCInsts automatically.
Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D155620
2023-07-19 11:30:56 +01:00
Ivan Kosarev
7b6e606dac [AMDGPU][AsmParser][NFC] Translate parsed MIMG instructions to MCInsts automatically.
Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D155061
2023-07-13 19:47:31 +01:00
Ivan Kosarev
289ae6525d [AMDGPU][MC] Fix handling of A16 operands in intersect_ray instructions.
The patch adds the support for 'noa16' operands in non-A16 variants of
the instructions, fixes validation of A16 operands and eliminates the
custom conversion to MCInst.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D155057
2023-07-13 19:46:03 +01:00
Scott Linder
986001c827 [AMDGPU] Improve assembler + disassembler handling of kernel descriptors
* Relax the AsmParser to accept `.amdhsa_wavefront_size32 0` when the
  `.amdhsa_shared_vgpr_count` directive is present.
* Teach the KD disassembler to respect the setting of
  KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 when calculating the
  value of `.amdhsa_next_free_vgpr`.
* Teach the KD disassembler to disassemble COMPUTE_PGM_RSRC3 for gfx90a
  and gfx10+.
* Include "pseudo directive" comments for gfx10 fields which are not
  controlled by any assembler directive.
* Fix disassembleObject failure diagnostic in llvm-objdump to not
  hard-code a comment string, and to follow the convention of not
  capitalizing the first sentence.

Reviewed By: rochauha

Differential Revision: https://reviews.llvm.org/D128014
2023-07-06 21:20:51 +00:00
Ivan Kosarev
12460cf90f [AMDGPU][AsmParser] Simplify the implementation of SWZ operands.
Those are implicit helper operands and therefore don't need any parsers
or printers.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: piotr, foad

Differential Revision: https://reviews.llvm.org/D154432
2023-07-05 10:45:12 +01:00
Ivan Kosarev
dac5957ca9 [AMDGPU][AsmParser][NFC] Clean up the implementation of KImmFP operands.
addKImmFPOperands() duplicates the KImmFP-specific logic implemented in
addLiteralImmOperand() and therefore can be removed.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D154427
2023-07-05 10:43:41 +01:00
Ivan Kosarev
ee165cdb1b [AMDGPU] Eliminate SIMCCodeEmitter and de-virtualise encoding methods.
Simplifies some future changes needed for
<https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D154337
2023-07-05 10:13:33 +01:00
Sergei Barannikov
d73c8c8fab [AMDGPU] Replace OperandMatchResultTy with ParseStatus (NFC)
ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:
```
  return Error(L, "msg");
```
when with MatchOperandResultTy it had to be:
```
  Error(L, "msg");
  return MatchOperand_ParseFail;
```
It also has more appropriate name since parse* methods are not only for
parsing operands.

Reviewed By: kosarev

Differential Revision: https://reviews.llvm.org/D154293
2023-07-04 22:29:56 +03:00
Ivan Kosarev
1ef47165fd [AMDGPU][AsmParser][NFC] Remove an unused function.
Was added in <https://reviews.llvm.org/D63293>, but never used.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D154331
2023-07-04 11:33:17 +01:00
Ivan Kosarev
b7e8a55a83 [AMDGPU][AsmParser][NFC] Simplify parsing of sopp_brtarget operands.
Also refine the definitions while there.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: mbrkusanin

Differential Revision: https://reviews.llvm.org/D154061
2023-06-30 16:35:46 +01:00
Ivan Kosarev
59fd48d71e [AMDGPU][AsmParser][NFC] Simplify instruction operand definitions.
This addresses the trivial cases that only require removing the
operand classes and renaming related entities.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D153965
2023-06-29 10:51:44 +01:00
Ivan Kosarev
5183ca8779 [AMDGPU][AsmParser] Eliminate cvtMtbuf().
Now that we have proper support for optional operands, the standard LLVM
machinery can take care of converting parsed instructions to MCInsts.
There are likely more cases where the conversion can be done
automatically, probably with some additional treatment. The plan is to
address them separately.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: arsenm, foad

Differential Revision: https://reviews.llvm.org/D153565
2023-06-23 12:43:52 +01:00
Ivan Kosarev
e95457d25b [AMDGPU][AsmParser][NFC] Simplify v_interp-related operand definitions.
Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D152897
2023-06-15 11:04:56 +01:00
Ivan Kosarev
024e540896 [AMDGPU][AsmParser][NFC] Get rid of custom default operand handlers.
Removes the need to add and remove them manually depending on whether
they are used in cvt*() functions. Also removes the compiler warnings
about unused handlers when it happens to be the case.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D151688
2023-06-14 12:10:56 +01:00
Ivan Kosarev
616d30c2cc [AMDGPU][AsmParser][NFC] Simplify the EndpgmImm operand definition.
Clears the road to eliminating custom default operand handlers. Also
unifies naming of related entities.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D151687
2023-06-13 18:46:08 +01:00
Ivan Kosarev
a3a8cbffcf [AMDGPU][AsmParser][NFC] Refine parsing of NamedOperandU32 operands.
Eliminates the need for the custom code in parseCustomOperand().

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D150980
2023-05-29 17:01:44 +01:00
Ivan Kosarev
212af2c081 [AMDGPU][AsmParser] Refine parsing of some 32-bit instruction operands.
Eliminates the need for the custom code in parseCustomOperand().

The remaining uses of NamedOperandU32 are to be addressed separately.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D150204
2023-05-19 16:54:30 +01:00
Diana Picus
bcbd9b021a [AMDGPU][MC] Don't accept attr > 32 for param_load
The docs say the interpolation attribute should be between 0..32 [1][2],
but we currently accept values all the way up to 63.

This patch makes the ASMParser error out for values > 32. It does not
touch codegen though because we're currently not checking anything at
all for codegen (llvm.amdgcn.lds.param.load will happily accept even 128
as an attr, although that won't fit in the encoding).

[1] https://llvm.org/docs/AMDGPU/gfx8_attr.html#amdgpu-synid-gfx8-attr
[2] https://llvm.org/docs/AMDGPU/gfx11_attr.html#amdgpu-synid-gfx11-attr

Differential Revision: https://reviews.llvm.org/D150261
2023-05-15 08:32:11 +02:00
Diana Picus
7591a7b6ea [AMDGPU][MC] Clean up DPP bound_ctrl handling
At the moment, we set the BC bit in DPP for both bound_ctrl:0 and
bound_ctrl:1, for compatibility with sp3 (see PR35397). However, this
hack is only needed for GFX8. For newer GFXs, sp3 behaves as expected,
i.e. it sets the bit when bound_ctrl:1 and clears it when bound_ctrl:0.

This patch updates LLVM to do the same for GFX11 or newer. We preserve
the current behaviour for GFX9 and 10 so we don't break any existing
code.

Differential Revision: https://reviews.llvm.org/D149254
2023-05-10 11:40:53 +02:00
NAKAMURA Takumi
c1221251fb Restore CodeGen/MachineValueType.h from Support
This is rework of;

  - rG13e77db2df94 (r328395; MVT)

Since `LowLevelType.h` has been restored to `CodeGen`, `MachinveValueType.h`
can be restored as well.

Depends on D148767

Differential Revision: https://reviews.llvm.org/D149024
2023-05-03 00:13:20 +09:00
Jay Foad
735cb7b1f8 [AMDGPU] Avoid using tuple where pair does suffice
Fixes the following building errors, happening with official Android prebuilt clang 14 shipped with Android 13:

external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:5491:13: error: no viable constructor or deduction guide for deduction of template arguments of 'tuple'
          ? std::tuple(HSAMD::V3::AssemblerDirectiveBegin,
            ^
...
external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:5493:13: error: no viable constructor or deduction guide for deduction of template arguments of 'tuple'
          : std::tuple(HSAMD::AssemblerDirectiveBegin,
            ^

Fixes: 6443c0e ("[AMDGPU] Stop using make_pair and make_tuple. NFC.")

Patch by Mauro Rossi!

Differential Revision: https://reviews.llvm.org/D142839
2023-04-21 08:30:35 +01:00
Ivan Kosarev
32f6b6bff5 [AMDGPU][AsmParser] Refine parsing SDWA operands.
Removes the need for the custom code in parseCustomOperand().

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D147241
2023-04-18 15:26:15 +01:00
Ivan Kosarev
5114843983 [AMDGPU][AsmParser] Refine SMRD offset definitions.
- Fixes the type of default 8-bit offset operands.
- Adds a test for optional offsets.

This is effectively an NFC.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D142231
2023-03-30 15:29:41 +01:00
Kazu Hirata
7ada7bbee1 [Target] Use *{Set,Map}::contains (NFC) 2023-03-14 18:06:55 -07:00
Jay Foad
dc3882eace [AMDGPU] Fix .amdhsa_shared_vgpr_count error checking for GFX11
Differential Revision: https://reviews.llvm.org/D145936
2023-03-14 09:05:32 +00:00
Ivan Kosarev
b06e5ad8a6 [AMDGPU][AsmParser][NFC] Simplify parsing cache policies.
Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D144954
2023-03-01 12:34:21 +00:00
Ivan Kosarev
905fa15d84 [AMDGPU][AsmParser] Distinguish literal and modifier SMEM offsets.
Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D144902
2023-02-28 12:58:54 +00:00
Mirko Brkusanin
b3dc0e69cf [AMDGPU][MC][GFX11] Add Partial NSA format for image sample instructions
Image sample instructions that need more than 5 VGPRs for VAddr can use
partial NSA for NSA encoding format. VGPRs that can not fit into the
encoding are sequential after the last one.
This patch adds assembly and disassembly parts.

Differential Revision: https://reviews.llvm.org/D144033
2023-02-23 13:33:34 +01:00
Changpeng Fang
7ca3444fba AMDGPU: Use module flag to get code object version at IR level folow-up
Summary:
  This is part of the leftover work for https://reviews.llvm.org/D143138.
In this work, we pass code object version as an argument to initialize target ID
and use it for targetID dump.

Reviewers: arsenm

Differential Revision
  https://reviews.llvm.org/D143293
2023-02-10 11:16:38 -08:00
Ivan Kosarev
f0f8ae7596 [AMDGPU][AsmParser] Fix matching immediate literals.
Prevents potential matching of literal offsets to non-literal operands.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D142194
2023-02-10 11:36:07 +00:00
Archibald Elliott
8e3d7cf5de [NFC][TargetParser] Remove llvm/Support/TargetParser.h 2023-02-07 11:08:21 +00:00
Changpeng Fang
54cf69c9d5 AMDGPU: Use module flag to get code object version at IR level
Summary:
  This patch introduces a mechanism to check the code object version from the module flag, This avoids checking from command line.
In case the module flag is missing, we use the current default code object version supported in the compiler.

For tools whose inputs are not IR, we may need other approach (directive, for example) to check the code
object version, That will be in a separate patch later.

For LIT tests update, we directly add module flag if there is only a single code object version associated with all checks in one file.
In cause of multiple code object version in one file, we use the "sed" method to "clone" the checks to achieve the goal.

Reviewer: arsenm

Differential Revision:
  https://reviews.llvm.org/D14313
2023-02-02 18:57:26 -08:00
Fangrui Song
7d3a181c8c [MC] Simplify code with parseComma 2023-02-01 18:41:02 -08:00
Jay Foad
073401e59c [MC] Define and use MCInstrDesc implicit_uses and implicit_defs. NFC.
The new methods return a range for easier iteration. Use them everywhere
instead of getImplicitUses, getNumImplicitUses, getImplicitDefs and
getNumImplicitDefs. A future patch will remove the old methods.

In some use cases the new methods are less efficient because they always
have to scan the whole uses/defs array to count its length, but that
will be fixed in a future patch by storing the number of implicit
uses/defs explicitly in MCInstrDesc. At that point there will be no need
to 0-terminate the arrays.

Differential Revision: https://reviews.llvm.org/D142215
2023-01-23 14:44:58 +00:00
Jay Foad
768aed1378 [MC] Make more use of MCInstrDesc::operands. NFC.
Change MCInstrDesc::operands to return an ArrayRef so we can easily use
it everywhere instead of the (IMHO ugly) opInfo_begin and opInfo_end.
A future patch will remove opInfo_begin and opInfo_end.

Also use it instead of raw access to the OpInfo pointer. A future patch
will remove this pointer.

Differential Revision: https://reviews.llvm.org/D142213
2023-01-23 11:31:41 +00:00
Kazu Hirata
caa99a01f5 Use llvm::popcount instead of llvm::countPopulation(NFC) 2023-01-22 12:48:51 -08:00
Ivan Kosarev
ce1aae4d54 [AMDGPU][AsmParser][NFC] Refine defining single-bit custom operands.
Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D141301
2023-01-16 16:11:59 +00:00
Ivan Kosarev
9976127605 [AMDGPU][AsmParser][NFC] Refine defining i8- and i16-typed custom operands.
Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D140799
2023-01-13 09:49:58 +00:00
Jay Foad
f460c66581 [AMDGPU] Simplify getNumFlatOffsetBits. NFC.
Previously we considered this field to be either N-bit unsigned or
N+1-bit signed, depending on the instruction. I think it's conceptually
simpler to say that the field is always N+1-bit signed, but some
instructions do not allow negative values.

Differential Revision: https://reviews.llvm.org/D140883
2023-01-12 10:40:36 +00:00
Ivan Kosarev
2d945ef864 [AMDGPU][NFC] Rename GFX10A16 operands.
They do not seem to be GFX10-specific anymore. Also renames the
corresponding feature.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D141069
2023-01-09 17:18:46 +00:00
serge-sans-paille
38818b60c5
Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part
Use deduction guides instead of helper functions.

The only non-automatic changes have been:

1. ArrayRef(some_uint8_pointer, 0) needs to be changed into ArrayRef(some_uint8_pointer, (size_t)0) to avoid an ambiguous call with ArrayRef((uint8_t*), (uint8_t*))
2. CVSymbol sym(makeArrayRef(symStorage)); needed to be rewritten as CVSymbol sym{ArrayRef(symStorage)}; otherwise the compiler is confused and thinks we have a (bad) function prototype. There was a few similar situation across the codebase.
3. ADL doesn't seem to work the same for deduction-guides and functions, so at some point the llvm namespace must be explicitly stated.
4. The "reference mode" of makeArrayRef(ArrayRef<T> &) that acts as no-op is not supported (a constructor cannot achieve that).

Per reviewers' comment, some useless makeArrayRef have been removed in the process.

This is a follow-up to https://reviews.llvm.org/D140896 that introduced
the deduction guides.

Differential Revision: https://reviews.llvm.org/D140955
2023-01-05 14:11:08 +01:00
Jay Foad
6f7ff9b933 [MC] Consistently use MCInstrDesc::getImplicitUses and getImplicitDefs. NFC. 2023-01-04 13:16:12 +00:00
Ivan Kosarev
0a6dc9a816 [AMDGPU][AsmParser] Refine parsing cache policy modifiers.
Reviewed By: dp, arsenm

Differential Revision: https://reviews.llvm.org/D140108
2022-12-30 15:44:34 +00:00
Sergei Barannikov
4d48ccfc88 [MC] Use MCRegister instead of unsigned in MCTargetAsmParser
Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D140273
2022-12-18 12:12:05 -08:00
Jay Foad
6443c0ee02 [AMDGPU] Stop using make_pair and make_tuple. NFC.
C++17 allows us to call constructors pair and tuple instead of helper
functions make_pair and make_tuple.

Differential Revision: https://reviews.llvm.org/D139828
2022-12-14 13:22:26 +00:00
Fangrui Song
67819a72c6 [CodeGen] llvm::Optional => std::optional 2022-12-13 09:06:36 +00:00