14 Commits

Author SHA1 Message Date
Craig Topper
1f395115da [RISCV] Add Zicond instructions to RISCVOptWInstrs like XVentanaCondOps. 2023-08-23 16:57:16 -07:00
Craig Topper
e28307e93a [RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
This removes selectSETCC and adds isel patterns for seteq/setne
conditions.

This removes the duplication of selectSETCC between lowering and
isel. This also gets some cases in xaluo.ll that we missed previously.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D156250
2023-07-26 10:06:08 -07:00
Craig Topper
f6dc75cdd8 [RISCV] Add DAG combine to pull xor with 1 through select idiom that uses czero_eqz/nez.
If we are selecting between two setccs that need to be legalized
with xor, the select will be legalized first. Detect this pattern
so we can pull the xor through to expose it to additional
optimizations.

We could generalize this to other operations, but those normally
get handled in DAG combine before select legalization.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D156159
2023-07-25 09:13:24 -07:00
Craig Topper
5ff5dac852 [RISCV] Add simple DAG combine to pull xor with 1 through select_cc.
If we're selecting the result of two setccs that have been legalized
by introducing an xor with 1, we can pull the xor with 1 through the
select to enable more optimizations.

We could generalize this to other binary operators with identical
conditions, but those are usually caught before we legalize the select.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D156144
2023-07-25 09:03:45 -07:00
Craig Topper
5990199e2c [RISCV] Add CZERO_EQZ/CZERO_NEZ to ComputeNumSignBitsForTargetNode.
Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D156082
2023-07-24 07:43:02 -07:00
Craig Topper
82686d7d55 [RISCV] Add test case for D156082 to condops.ll
This test is copied from select-cc.ll. It wasn't worth adding
Zicond RUN lines to that file.

Reviewed By: asb, wangpc

Differential Revision: https://reviews.llvm.org/D156083
2023-07-24 07:42:46 -07:00
Craig Topper
7dfe62327d [RISCV] Add a DAG combine for (czero_eq X, (xor Y, 1)) -> (czero_ne X, Y) if Y is 0 or 1.
This is an alternative to D155288 that can handle other sources of
xori like FP compares. Unfortunately, it misses the i64 setge case
on RV32 in condops.ll.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D155328
2023-07-19 12:33:08 -07:00
Craig Topper
0c055286b2 [RISCV] Use RISCVISD::CZERO_EQZ/CZERO_NEZ for XVentanaCondOps.
This makes Zicond and XVentanaCondOps use the same code path.
The instructions have identical semantics.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D155391
2023-07-18 10:18:02 -07:00
Craig Topper
fda45d9198 [RISCV] Add FP compare test to condops.ll to show a missed opportunity to remove an xori. NFC
This is a case that D155288 won't get.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D155327
2023-07-17 08:47:42 -07:00
Alex Bradbury
95075d3d2c [RISCV][test] Add RV32I and RV64I RUN lines to condops.ll test
Some of these test cases will be changed by upcoming combines, even in
the non-zicond case.
2023-07-14 13:29:40 +01:00
Alex Bradbury
5c5a1a2927 [RISCV] Introduce RISCVISD::CZERO_{EQZ,NEZ} nodes produce them when zicond is present in lowerSELECT
This patch is a step towards altering how we handle the emission of
condops. Marking ISD::SELECT as legal is a major change in the codegen
path, and gives few options for maintaining the old codegen path when
it is believed to be better (e.g. a better branchless sequence is
possible using non-zicond instructions, or the branch-based sequence is
preferable).

This removes the existing SelectionDAG patterns and moves the logic into
lowerSELECT. Along some small codegen changes you'll note a few minor
regressions in the generated code quality - this are due to the fact
that by lowering the SELECT node early we miss out on combines that
would kick in later when setcc condcodes that aren't natively supported
have been expanded (thus exposing opportunities for optimisation by
performing logical negation and swapping truev/falsev). I've opted to
split out work that addresses these into follow-on patches (especially
as zicond is still 'experimental').

matchSetCC is a straight-forward translation from the version in
RISCVISelDAGToDAG. Ideally, in the future it can be converted to a
helper shared between both files.

Differential Revision: https://reviews.llvm.org/D155083
2023-07-14 11:31:27 +01:00
Mikhail Gudim
17e2df6695 [RISCV] Removed the requirement of XLenVT for performSELECTCombine.
Reviewed By: Craig Topper

Differential Revision: https://reviews.llvm.org/D153044
2023-07-12 16:29:09 -04:00
Alex Bradbury
a755e80ed1 [RISCV] Add codegen for the experimental zicond extension
This directly matches the codegen for xventanacondops with vt.maskcn =>
czero.nez and vt.maskc => czero.eqz. An additional difference is that
zicond is available on RV32 in addition to RV64 (xventanacondops is RV64
only).

Differential Revision: https://reviews.llvm.org/D147147
2023-03-30 21:05:22 +01:00
Philipp Tomsich
f68f04d07c [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144681
2023-02-24 21:40:42 +01:00