14 Commits

Author SHA1 Message Date
Weiwei Chen
2b2889b723 Add index::CmpOp canonicalization.
Add canonicalization pattern for index::CmpOp

Differential Revision: https://reviews.llvm.org/D157903
2023-08-14 22:56:28 -04:00
Jeff Niu
8aa16d1921 [mlir][index] Add identity folders for add and sub
Depends on D153736

Reviewed By: rriddle, jpienaar

Differential Revision: https://reviews.llvm.org/D153780
2023-06-26 11:49:16 -07:00
Jeff Niu
42092c071a [mlir][index] Add index.mul identity folders
Fold `mul(x, 1)` and `mul(x, 0)`.

Depends on D153736

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D153736
2023-06-26 11:49:13 -07:00
Jeff Niu
962f71be5a [mlir][index] Fold cmp(max/min(x, cstA), cstB)
This is a case that is not picked up by integer range inference and
suggests a weakness with integer range inference on the index dialect.
The problem is that when `[1, SMAX_64]` is truncated to 32 bits, the
resulting range could be `[SMIN_32, SMAX_32]`, making the subsequent
comparison worthless. This is because integer range inference doesn't
know that the result of the max/min inference also changes based on the
bitwidth, and doing the truncation locally at the input of the
comparison op loses that information.

This also was a pattern that frequently showed up in our code, so adding
it as a folder allows dead code to be pruned more frequently.

Depends on D153731

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D153732
2023-06-26 11:49:09 -07:00
rikhuijzer
2e4e218474 [mlir] Avoid folding index.remu and index.rems for 0 rhs
As discussed in https://github.com/llvm/llvm-project/issues/59714#issuecomment-1369518768, the folder for the remainder operations should be resillient when the rhs is 0.
The file `IndexOps.cpp` was already checking for multiple divisions by zero, so I tried to stick to the code style from those checks.

Fixes #59714.

As a side note, is it correct that remainder operations are never optimized away? I would expect that the following code

```
func.func @remu_test() -> index {
  %c3 = index.constant 2
  %c0 = index.constant 1
  %0 = index.remu %c3, %c0
  return %0 : index
}
```
would be optimized to
```
func.func @remu_test() -> index {
  return index.constant 0 : index
}
```
when called with `mlir-opt --convert-scf-to-openmp temp.mlir`, but maybe I'm misunderstanding something.

Reviewed By: Mogball

Differential Revision: https://reviews.llvm.org/D151476
2023-05-31 10:45:26 -07:00
Krzysztof Drewniak
5af9d16dae [mlir][Index] Implement InferIntRangeInterface, re-land
Re-land D140899 to fix a missing dependency in the index dialect's
CMakeLists.txt.

Reviewed By: Mogball

Differential Revision: https://reviews.llvm.org/D142147
2023-01-20 20:32:30 +00:00
Krzysztof Drewniak
9f59affa24 Revert "[mlir][Index] Implement InferIntRangeInterface"
This reverts commit 455305624884cf9237143e2ba0635fcc5ba5206a.

Linker error, unbreak build while I work out how to fix it.

Differential Revision: https://reviews.llvm.org/D142142
2023-01-19 18:43:12 +00:00
Krzysztof Drewniak
4553056248 [mlir][Index] Implement InferIntRangeInterface
Implement InferIntRangeInterface for all operations in the Index dialect. The
inference implementation, unlike the one for Arith, accounts for the
fact that Index can be either 64 or 32 bits long by evaluating both
cases. Bounds are stored as if index were i64, but when inferring new
bounds, we compute both f(...) and f(trunc(...)). We then compare
trunc(f(...)) to f(trunc(...)). If they are equal in the relevant
range components, we use the 64-bit range computation, otherwise we
give the range ext(f(trunc(...))) union f(...).

Note that this can cause surprising behavior as seen in the tests,
where, for example, the order of min and max operations impacts the
behavior of the inference. The inference could perhaps be made more
precise in the future (ex. by tracking 32 and 64-bit results
separately and having them influence each other somehow) butt, since
my project targets an index=i32 platform and doesn't see index-valued
values > uint32_max, I'm not too concerned about it.

Depends on https://reviews.llvm.org/D141299

Depends on https://reviews.llvm.org/D141296

Reviewed By: Mogball

Differential Revision: https://reviews.llvm.org/D140899
2023-01-19 17:48:24 +00:00
Krzysztof Drewniak
8cdb4f9f66 [mlir][Index] Add index.mins and index.minu
Signed and unsigned minimum operations were missing from the Index
dialect and are needed to test integer range inference.

Reviewed By: Mogball

Differential Revision: https://reviews.llvm.org/D141299
2023-01-10 21:41:59 +00:00
River Riddle
ac9f88e862 [mlir][Index] Add pretty result names for ConstantOp and BoolConstantOp
ConstantOp uses `%idx<value>` and BoolConstantOp uses true/false, which
is similar to the printing for arith::ConstantOp.

Differential Revision: https://reviews.llvm.org/D139175
2022-12-02 01:34:29 -08:00
Luca Boasso
4f9c9295a6 [mlir][index] Add and, or, and xor ops
This patch adds the and, or, and xor bitwise operations to
the index dialects with folders and LLVM lowerings.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D138590
2022-11-23 13:26:02 -06:00
Jeff Niu
9ef3146511 [mlir][index] Add shl, shrs, and shru ops
This patch adds the left shift, signed right shift, and unsigned right
shift operations to the index dialects with folders and LLVM lowerings.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D137349
2022-11-03 16:29:04 -07:00
Jeff Niu
83c3eebdec [mlir][index] Add folders for index ops
This patch adds folders for `index` dialect ops. Ths folders are
careful to ensure that fold results are valid on both 32-bit and 64-bit
targets.

Depends on D135689

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D135694
2022-10-21 09:46:12 -07:00
Jeff Niu
ddf87d6cd4 [mlir][index] Add index dialect ops and attributes
This patch adds the definitions for the operations and attributes (just
one enum attribute) for the `index` dialect.

Depends on D135688

Reviewed By: rriddle, jpienaar

Differential Revision: https://reviews.llvm.org/D135689
2022-10-21 09:46:06 -07:00