2 Commits

Author	SHA1	Message	Date
Alex Bradbury	a755e80ed1	[RISCV] Add codegen for the experimental zicond extension ... This directly matches the codegen for xventanacondops with vt.maskcn => czero.nez and vt.maskc => czero.eqz. An additional difference is that zicond is available on RV32 in addition to RV64 (xventanacondops is RV64 only). Differential Revision: https://reviews.llvm.org/D147147	2023-03-30 21:05:22 +01:00
Philipp Tomsich	f68f04d07c	[RISCV] Add vendor-defined XTheadCondMov (conditional move) extension ... The vendor-defined XTheadCondMov (somewhat related to the upcoming Zicond and XVentanaCondOps) extension add conditional move instructions with $rd being an input and an ouput instructions. It is supported by the C9xx cores (e.g., found in the wild in the Allwinner D1) by Alibaba T-Head. The current (as of this commit) public documentation for this extension is available at: https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf Support for these instructions has already landed in GNU Binutils: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D144681	2023-02-24 21:40:42 +01:00