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1969 Commits

Author SHA1 Message Date
Eric Christopher
0713a9d8fc Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Eric Christopher
354b2a25f3 Make the Uv constraint a memory operand. This doesn't solve the 
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939

llvm-svn: 132561
 2011-06-03 17:24:37 +00:00
Eric Christopher
de9399bf76 Have LowerOperandForConstraint handle multiple character constraints. 
Part of rdar://9119939

llvm-svn: 132510
 2011-06-02 23:16:42 +00:00
John McCall
7d84ece09b On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

Take 2, now with more basic competence.

llvm-svn: 132295
 2011-05-29 19:50:32 +00:00
John McCall
e64371b932 I didn't mean to commit these residues of a personal project. 
llvm-svn: 132293
 2011-05-29 19:41:56 +00:00
John McCall
085d891d80 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

llvm-svn: 132291
 2011-05-29 19:39:04 +00:00
Bruno Cardoso Lopes
325110f30d Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs 
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

llvm-svn: 132248
 2011-05-28 04:07:29 +00:00
Cameron Zwarich
1d553a2cc4 Fix the remaining atomic intrinsics to use the right register classes on Thumb2, 
and add some basic tests for them.

llvm-svn: 132235
 2011-05-27 23:54:00 +00:00
Evan Cheng
518bcd0ef4 Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789 
llvm-svn: 132211
 2011-05-27 20:11:27 +00:00
Renato Golin
4cd5187f5b RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller. 
llvm-svn: 131868
 2011-05-22 21:41:23 +00:00
Evan Cheng
4fcd8250ae Revert accidental commit. 
llvm-svn: 131739
 2011-05-20 17:38:48 +00:00
Evan Cheng
e8d2e9eb35 Revert r131664 and fix it in instcombine instead. rdar://9467055 
llvm-svn: 131708
 2011-05-20 00:54:37 +00:00
Mon P Wang
6d9e1c7c2e Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change. 
llvm-svn: 131630
 2011-05-19 04:15:07 +00:00
Tanya Lattner
1d11720ae4 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.

llvm-svn: 131582
 2011-05-18 21:44:54 +00:00
Evan Cheng
522fbfea3b Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159. 
llvm-svn: 131555
 2011-05-18 18:59:17 +00:00
Evan Cheng
80632c91b0 Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 
llvm-svn: 131553
 2011-05-18 18:47:27 +00:00
Tanya Lattner
48b182c3a4 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.

llvm-svn: 131529
 2011-05-18 06:42:21 +00:00
Cameron Zwarich
f9839e4257 Fix typo. 
llvm-svn: 131519
 2011-05-18 02:29:50 +00:00
Cameron Zwarich
d7c55fe2ef Fix more of PR8825 by correctly using rGPR registers when lowering atomic 
compare-and-swap intrinsics.

llvm-svn: 131518
 2011-05-18 02:20:07 +00:00
Bill Wendling
50117f8186 Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp 
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>

llvm-svn: 131174
 2011-05-11 01:11:55 +00:00
Eli Friedman
2518f8376d Make the logic for determining function alignment more explicit. No functionality change. 
llvm-svn: 131012
 2011-05-06 20:34:06 +00:00
Bob Wilson
09585e1c5d Temporarily disable use of divmod compiler-rt functions for iOS. 
llvm-svn: 130766
 2011-05-03 17:33:22 +00:00
Dan Gohman
6136e94897 Add an unfolded offset field to LSR's Formula record. This is used to 
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.

llvm-svn: 130743
 2011-05-03 00:46:49 +00:00
Eric Christopher
e02e07c3a6 80-col. 
llvm-svn: 130558
 2011-04-29 23:12:01 +00:00
Jim Grosbach
d4b733e4d8 ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads. 
rdar://9326019

llvm-svn: 130234
 2011-04-26 19:44:18 +00:00
Andrew Trick
0ed5778a1e Thumb2 and ARM add/subtract with carry fixes. 
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.

Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.

Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).

llvm-svn: 130048
 2011-04-23 03:55:32 +00:00
Evan Cheng
5f1ba4cd2d Remove -use-divmod-libcall. Let targets opt in when they are available. 
llvm-svn: 129884
 2011-04-20 22:20:12 +00:00
Stuart Hastings
7850af6ea0 Excise unintended hunk in 129858. <rdar://problem/7662569> 
llvm-svn: 129862
 2011-04-20 18:09:26 +00:00
Stuart Hastings
45fe3c38c5 ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569> 
llvm-svn: 129858
 2011-04-20 16:47:52 +00:00
Eric Christopher
c721b0db6d Remove some duplicate op action entries and reorganize. 
llvm-svn: 129781
 2011-04-19 18:49:19 +00:00
Chris Lattner
0ab5e2cded Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Evan Cheng
12bb05b75b Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't 
forget to right shift the source by 32 first. rdar://9287902

llvm-svn: 129556
 2011-04-15 01:31:00 +00:00
Cameron Zwarich
415b5e8341 Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>. 
llvm-svn: 129468
 2011-04-13 21:01:19 +00:00
Cameron Zwarich
fbcd69b96a Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM 
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

llvm-svn: 129345
 2011-04-12 02:24:17 +00:00
Evan Cheng
74d92c1924 Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time. 
llvm-svn: 129152
 2011-04-08 21:37:21 +00:00
Evan Cheng
9a3f2772f0 Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
llvm-svn: 129107
 2011-04-07 20:31:12 +00:00
Tanya Lattner
266792a55a Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases. 
llvm-svn: 129074
 2011-04-07 15:24:20 +00:00
Evan Cheng
a7c7b54dde Change -arm-divmod-libcall to a target neutral option. 
llvm-svn: 129045
 2011-04-07 00:58:44 +00:00
Owen Anderson
867846b1f0 Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding. 
llvm-svn: 128965
 2011-04-05 23:55:28 +00:00
Owen Anderson
61e7a935bd Revert r128946 while I figure out why it broke the buildbots. 
llvm-svn: 128951
 2011-04-05 23:03:06 +00:00
Owen Anderson
3501655ad9 Give RSBS and RSCS the pseudo treatment. 
llvm-svn: 128946
 2011-04-05 22:42:54 +00:00
Owen Anderson
77aa266de8 Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. 
llvm-svn: 128940
 2011-04-05 21:48:57 +00:00
Bill Wendling
dd4dcd549b Revamp the SjLj "dispatch setup" intrinsic. 
It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>

llvm-svn: 128873
 2011-04-05 01:37:43 +00:00
Cameron Zwarich
6fe5c29430 Do some peephole optimizations to remove pointless VMOVs from Neon to integer 
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.

llvm-svn: 128759
 2011-04-02 02:40:43 +00:00
Evan Cheng
bd76679700 Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs. 
rdar://8911343

llvm-svn: 128696
 2011-04-01 00:42:02 +00:00
Evan Cheng
38bf5adcea Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier 
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

llvm-svn: 128665
 2011-03-31 19:38:48 +00:00
Evan Cheng
ee9d45dd55 Don't try to create zero-sized stack objects. 
llvm-svn: 128586
 2011-03-30 23:44:13 +00:00
Cameron Zwarich
53dd03d537 Add a ARM-specific SD node for VBSL so that forms with a constant first operand 
can be recognized. This fixes <rdar://problem/9183078>.

llvm-svn: 128584
 2011-03-30 23:01:21 +00:00
Evan Cheng
18381b4257 Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends 
was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.

Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.

First part of rdar://8832507, rdar://9203134

llvm-svn: 128502
 2011-03-29 23:06:19 +00:00
Cameron Zwarich
143f9aea2b Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. Fixes 
<rdar://problem/8875309> and <rdar://problem/9057191>.

llvm-svn: 128492
 2011-03-29 21:41:55 +00:00