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1969 Commits

Author SHA1 Message Date
Bob Wilson
91fdf68516 Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by 
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.

llvm-svn: 104415
 2010-05-22 00:23:12 +00:00
Evan Cheng
34c260458a Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). 
llvm-svn: 104307
 2010-05-21 00:43:17 +00:00
Evan Cheng
4401f8873c Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
llvm-svn: 104293
 2010-05-20 23:26:43 +00:00
Bob Wilson
5954994bba Handle Neon v2f64 and v2i64 vector shuffles as register copies. 
This fixes the remaining issue with pr7167.

llvm-svn: 104257
 2010-05-20 18:39:53 +00:00
Evan Cheng
738e920edf Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. 
llvm-svn: 104147
 2010-05-19 20:19:50 +00:00
Evan Cheng
f19384d54a Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 
llvm-svn: 104060
 2010-05-18 21:31:17 +00:00
Anton Korobeynikov
4c719c4515 Generalize the ARM DAG combiner of mul with constants to all power-of-two cases. 
llvm-svn: 103901
 2010-05-16 08:54:20 +00:00
Anton Korobeynikov
1bf28a128b Some cheap DAG combine goodness for multiplication with a particular constant. 
This can be extended later on to handle more "complex" constants.

llvm-svn: 103881
 2010-05-15 18:16:59 +00:00
Evan Cheng
3d214cdfaf v4i64 and v8i64 are only synthesizable when NEON is available. 
llvm-svn: 103855
 2010-05-15 02:20:21 +00:00
Evan Cheng
4cad68eb34 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854
 2010-05-15 02:18:07 +00:00
Evan Cheng
cd67c21407 Added a QQQQ register file to model 4-consecutive Q registers. 
llvm-svn: 103760
 2010-05-14 02:13:41 +00:00
Dan Gohman
bb919dfb6b Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481
 2010-05-11 17:31:57 +00:00
Evan Cheng
2fa5a7e7e4 Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
llvm-svn: 103459
 2010-05-11 07:26:32 +00:00
Evan Cheng
c2ae5f546f Model vld2 / vst2 with reg_sequence. 
llvm-svn: 103411
 2010-05-10 17:34:18 +00:00
Jim Grosbach
2a41cad900 Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277
 2010-05-07 18:34:55 +00:00
Jim Grosbach
151cd8f159 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Jim Grosbach
92d999001c Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119
 2010-05-05 20:44:35 +00:00
Evan Cheng
d85631e700 Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. 
llvm-svn: 103104
 2010-05-05 18:28:36 +00:00
Dan Gohman
25c1653700 Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.

llvm-svn: 102809
 2010-05-01 00:01:06 +00:00
Dan Gohman
21cea8ac2e Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
 2010-04-17 15:26:15 +00:00
Dan Gohman
31ae586c74 Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.

llvm-svn: 101634
 2010-04-17 14:41:14 +00:00
Bob Wilson
59b70eacad Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this 
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.

llvm-svn: 101615
 2010-04-17 05:30:19 +00:00
Evan Cheng
f7f97b4bbd Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. 
llvm-svn: 101410
 2010-04-15 22:20:34 +00:00
Anders Carlsson
47bccf7f28 Fix build. 
llvm-svn: 101335
 2010-04-15 03:11:28 +00:00
Dan Gohman
bcaf681cde Add const qualifiers to CodeGen's use of LLVM IR constructs. 
llvm-svn: 101334
 2010-04-15 01:51:59 +00:00
Jim Grosbach
32bb362655 Add -arm-long-calls option to force calls to be indirect. This makes the 
kernel linker happier when dealing with kexts.

Radar 7805069

llvm-svn: 101303
 2010-04-14 22:28:31 +00:00
Bob Wilson
c05b887c84 Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand 
does not have a legal type.  The legalizer does not know how to handle those
nodes.  Radar 7854640.

llvm-svn: 101282
 2010-04-14 20:45:23 +00:00
Bob Wilson
699bdf7adf Handle a v2f64 formal parameter that is split between registers and memory 
such that the entire second half is in memory.  Radar 7855014.

llvm-svn: 101181
 2010-04-13 22:03:22 +00:00
Bob Wilson
5202269dc4 Expand SELECT and SELECT_CC for NEON vector types. 
Radar 7770501.

llvm-svn: 100568
 2010-04-06 22:02:24 +00:00
Mon P Wang
c576ee9040 Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100304
 2010-04-04 03:10:48 +00:00
Mon P Wang
999c1b927b Revert r100191 since it breaks objc in clang 
llvm-svn: 100199
 2010-04-02 18:43:02 +00:00
Mon P Wang
a972ab8564 Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100191
 2010-04-02 18:04:15 +00:00
Bob Wilson
6f7fd28824 Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots. 
llvm-svn: 99948
 2010-03-30 22:27:04 +00:00
Mon P Wang
7460571381 Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, 
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.

llvm-svn: 99928
 2010-03-30 20:55:56 +00:00
Jim Grosbach
07607382d8 tweak the arm if conversion heuristic 
llvm-svn: 99402
 2010-03-24 16:15:14 +00:00
Jim Grosbach
e0874fa02f try being more permissive for if-conversion on ARM V7. see what the nightly 
test run permformance numbers say as to whether it helps.

llvm-svn: 99355
 2010-03-24 00:03:13 +00:00
Bob Wilson
e4191e719b Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010
 2010-03-19 22:51:32 +00:00
Anton Korobeynikov
f11aa9e7b4 Get rid of target-specific fp <-> int nodes when still I'm here. 
llvm-svn: 98889
 2010-03-18 22:35:45 +00:00
Anton Korobeynikov
64578d5599 Get rid of target-specific nodes for fp16 <-> fp32 conversion. 
llvm-svn: 98888
 2010-03-18 22:35:37 +00:00
Bob Wilson
3f2293bc02 Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass. 
Radar 7459078.

llvm-svn: 98586
 2010-03-15 23:09:18 +00:00
Bill Wendling
bbcaa40227 Now that the default for Darwin platforms is to place the LSDA into the TEXT 
section, remove the target-specific code that performs this.

llvm-svn: 98580
 2010-03-15 21:09:38 +00:00
Anton Korobeynikov
0a65a37344 Add substarget feature for FP16 
llvm-svn: 98503
 2010-03-14 18:42:38 +00:00
Anton Korobeynikov
d7fece38fc Add codegen support for FP16 on ARM 
llvm-svn: 98502
 2010-03-14 18:42:31 +00:00
Bill Wendling
9481181d40 The ARM EH experiment worked! 
Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.

llvm-svn: 98068
 2010-03-09 18:31:07 +00:00
Bill Wendling
46ffefc66c This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please 
bear with the awful code. It won't last in its current state beyond tonight.

llvm-svn: 98040
 2010-03-09 02:46:12 +00:00
Bill Wendling
78c5b7a76d Remove dead parameter passing. 
llvm-svn: 97536
 2010-03-02 01:55:18 +00:00
Bob Wilson
ba8ac74fd9 Check for comparisons of +/- zero when optimizing less-than-or-equal and 
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions.  This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.

llvm-svn: 97065
 2010-02-24 22:15:53 +00:00
Jim Grosbach
6ad4bcb0da LowerCall() should always do getCopyFromReg() to reference the stack pointer. 
Machine instruction selection is much happier when operands are in virtual
registers.

llvm-svn: 97012
 2010-02-24 01:43:03 +00:00
Bob Wilson
c6c13a3515 Use NEON vmin/vmax instructions for floating-point selects. 
Radar 7461718.

llvm-svn: 96572
 2010-02-18 06:05:53 +00:00
David Greene
0d0149f5ac Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96230
 2010-02-15 16:55:24 +00:00