2591 Commits

Author SHA1 Message Date
Sjoerd Meijer
357237e93e Recommit "[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode"
This reverts commit effc3b079927a6dd3084b4ff712ec07f926366f0, with the build
problem fixed.
2021-02-15 11:33:00 +00:00
Sjoerd Meijer
effc3b0799 Revert "[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode"
This reverts commit cd6de0e8de4a5fd558580be4b1a07116914fc8ed.
2021-02-15 11:01:23 +00:00
Sjoerd Meijer
cd6de0e8de [TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode
This refactors shouldFavorPostInc() and shouldFavorBackedgeIndex() into
getPreferredAddressingMode() so that we have one interface to steer LSR in
generating the preferred addressing mode.

Differential Revision: https://reviews.llvm.org/D96600
2021-02-15 10:44:15 +00:00
Kazu Hirata
910e2d1e57 [llvm] Use llvm::is_contained (NFC) 2021-02-14 08:36:20 -08:00
Sander de Smalen
703130fb01 [TTI] Change TargetTransformInfo::getMinimumVF to return ElementCount
This will be needed in the loop-vectorizer where the minimum VF
requested may be a scalable VF. getMinimumVF now takes an additional
operand 'IsScalableVF' that indicates whether a scalable VF is required.

Reviewed By: kparzysz, rampitec

Differential Revision: https://reviews.llvm.org/D96020
2021-02-11 09:08:48 +00:00
Simon Pilgrim
3c9073864c [Hexagon] Fix multiclass template parameter types. NFC.
Fixes TableGen parser errors reported by D95874.
2021-02-06 15:28:26 +00:00
Craig Topper
11ef356d9e [TargetLowering] Use Align in allowsMisalignedMemoryAccesses.
Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D96097
2021-02-04 19:22:06 -08:00
Krzysztof Parzyszek
0bb1985102 [Hexagon] Add LLVM instruction definitions for Hexagon V68 2021-02-03 13:59:34 -06:00
Kazu Hirata
0da15ea581 [llvm] Use append_range (NFC) 2021-01-27 23:25:41 -08:00
Kazu Hirata
054444177b [Target] Use llvm::append_range (NFC) 2021-01-24 12:18:56 -08:00
Kazu Hirata
e4847a7fcf Revert "[Target] Use llvm::append_range (NFC)"
This reverts commit cc7a23828657f35f706343982cf96bb6583d4d73.

The X86WinEHState.cpp hunk seems to break certain builds.
2021-01-23 11:25:27 -08:00
Kazu Hirata
cc7a238286 [Target] Use llvm::append_range (NFC) 2021-01-23 10:56:31 -08:00
Kazu Hirata
8857202489 [llvm] Use llvm::find (NFC) 2021-01-19 20:19:14 -08:00
Brendon Cahoon
57443bfb4a [Hexagon] Fix segment start to adjust for gaps between segments
The Hexagon Vector Combine pass genertes stores for a complete
aligned vector. The start of each section is a multiple of the
vector size, so that value is passed to normalize to compute
the offset of the stores in the section.  The first store may
not occur at offset 0 when there is a gap between sections.
2021-01-19 12:49:39 -06:00
Kazu Hirata
352fcfc697 [llvm] Use llvm::sort (NFC) 2021-01-17 10:39:45 -08:00
Kazu Hirata
2082b10d10 [llvm] Use *::empty (NFC) 2021-01-16 09:40:55 -08:00
Kazu Hirata
2efcbe24a7 [llvm] Use llvm::drop_begin (NFC) 2021-01-14 20:30:33 -08:00
Kazu Hirata
125ea20d55 [llvm] Use llvm::stable_sort (NFC) 2021-01-13 19:14:43 -08:00
Krzysztof Parzyszek
a2e6506c47 [Hexagon] Improve legalizing of ISD::SETCC result 2021-01-13 12:29:22 -06:00
Kazu Hirata
8a20e2b3d3 [llvm] Use Optional::getValueOr (NFC) 2021-01-12 21:43:50 -08:00
Krzysztof Parzyszek
a90214760d [Hexagon] Custom-widen SETCC's operands
The result cannot be widened, unfortunately, because widening vNi1
would depend on the context in which it appears (i.e. the type alone
is not sufficient to tell if it needs to be widened).
2021-01-11 12:21:49 -06:00
Bjorn Pettersson
675be65106 Require chained analyses in BasicAA and AAResults to be transitive
This patch fixes a bug that could result in miscompiles (at least
in an OOT target). The problem could be seen by adding checks that
the DominatorTree used in BasicAliasAnalysis and ValueTracking was
valid (e.g. by adding DT->verify() call before every DT dereference
and then running all tests in test/CodeGen).

Problem was that the LegacyPassManager calculated "last user"
incorrectly for passes such as the DominatorTree when not telling
the pass manager that there was a transitive dependency between
the different analyses. And then it could happen that an incorrect
dominator tree was used when doing alias analysis (which was a pretty
serious bug as the alias analysis result could be invalid).

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48709

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D94138
2021-01-11 11:50:07 +01:00
Arthur Eubanks
b2dafd44ca [NewPM][Hexagon] Fix HexagonVectorLoopCarriedReusePass position in pipeline
In https://reviews.llvm.org/D88138 this was incorrectly added with
registerOptimizerLastEPCallback(), when it should be
registerLoopOptimizerEndEPCallback(), matching the legacy PM's
EP_LoopOptimizerEnd.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D93929
2021-01-07 15:04:28 -08:00
Oliver Stannard
76f6b125ce Revert "[llvm] Use BasicBlock::phis() (NFC)"
Reverting because this causes crashes on the 2-stage buildbots, for
example http://lab.llvm.org:8011/#/builders/7/builds/1140.

This reverts commit 9b228f107d43341ef73af92865f73a9a076c5a76.
2021-01-07 09:43:33 +00:00
Kazu Hirata
9b228f107d [llvm] Use BasicBlock::phis() (NFC) 2021-01-06 18:27:35 -08:00
Krzysztof Parzyszek
46975b5b29 [Hexagon] Wrap functions only used in asserts in ifndef NDEBUG 2021-01-06 09:40:38 -06:00
Krzysztof Parzyszek
ee11bf316f [Hexagon] Silence unused function warning with gcc10, NFC 2021-01-05 14:11:45 -06:00
Krzysztof Parzyszek
c55b609b77 [Hexagon] Fix bad SDNodeXForm
Fixes https://llvm.org/PR48651
2021-01-04 10:43:01 -06:00
Kazu Hirata
985f899bf2 [Target] Use llvm::append_range (NFC) 2021-01-03 09:57:43 -08:00
Kazu Hirata
171c5fd43e [llvm] Use llvm::erase_value and llvm::erase_if (NFC) 2021-01-02 09:24:15 -08:00
Wang, Pengfei
16c2067cf2 [X86][AMX] Fix compilation warning introduced by 981a0bd8. 2020-12-30 22:22:13 +08:00
Juneyoung Lee
9b29610228 Use unary CreateShuffleVector if possible
As mentioned in D93793, there are quite a few places where unary `IRBuilder::CreateShuffleVector(X, Mask)` can be used
instead of `IRBuilder::CreateShuffleVector(X, Undef, Mask)`.
Let's update them.

Actually, it would have been more natural if the patches were made in this order:
(1) let them use unary CreateShuffleVector first
(2) update IRBuilder::CreateShuffleVector to use poison as a placeholder value (D93793)

The order is swapped, but in terms of correctness it is still fine.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D93923
2020-12-30 22:36:08 +09:00
Arthur O'Dwyer
22cf54a7fb Replace T(x) with reinterpret_cast<T>(x) everywhere it means reinterpret_cast. NFC.
Differential Revision: https://reviews.llvm.org/D76572
2020-12-22 19:54:29 -05:00
Kazu Hirata
966f1431de [Target] Use llvm::erase_if (NFC) 2020-12-20 17:43:22 -08:00
Krzysztof Parzyszek
fe0527e1c7 [Hexagon] Temporarily disable vector realignment for non-HVX vectors 2020-12-15 19:03:07 -06:00
Krzysztof Parzyszek
16385643bb [Hexagon] Emit enough stores when aligning vector addresses 2020-12-15 18:59:53 -06:00
Krzysztof Parzyszek
71601d2ac9 [Hexagon] Fix bitcasting v1i8 -> i8 2020-12-15 16:01:24 -06:00
Reid Kleckner
55fc64bce0 [Hexagon] Tweak _MSC_VER workaround version
My bot runs VS 2019, but it could not compile this code.

Message:
[55/2465] Building CXX object lib\Target\Hexagon\CMakeFiles\LLVMHexagonCodeGen.dir\HexagonVectorCombine.cpp.obj
FAILED: lib/Target/Hexagon/CMakeFiles/LLVMHexagonCodeGen.dir/HexagonVectorCombine.cpp.obj
...
C:\Program Files (x86)\Microsoft Visual Studio\2019\Professional\VC\Tools\MSVC\14.23.28105\include\map(71): error C2976: 'std::map': too few template arguments
C:\Program Files (x86)\Microsoft Visual Studio\2019\Professional\VC\Tools\MSVC\14.23.28105\include\map(71): note: see declaration of 'std::map'

The version in the path, 14.23, corresponds to _MSC_VER 1923, so raise
the version floor to 1924.

I have not tested with versions between 1924 and 1928 (latest), but the
latest works with the variadic version.
2020-12-14 11:26:36 -08:00
Kazu Hirata
913515e465 [Target] Use llvm::is_contained (NFC) 2020-12-13 19:35:10 -08:00
Krzysztof Parzyszek
baf931a842 [Hexagon] Reconsider getMask fix, return original mask, convert later
The getPayload/getMask/getPassThrough functions should return values
that could be composed into a masked load/store without any additional
type casts. The previous fix violated that.
Instead, convert scalar mask to a vector right before rescaling.
2020-12-12 13:27:22 -06:00
Krzysztof Parzyszek
2cf5310471 [Hexagon] Create vector masks for scalar loads/stores
AlignVectors treats all loaded/stored values as vectors of bytes,
and masks as corresponding vectors of booleans, so make getMask
produce a 1-element vector for scalars from the start.
2020-12-12 11:12:17 -06:00
Krzysztof Parzyszek
2d8cc5479b [Hexagon] Workaround for compilation error with VS2017 2020-12-11 15:11:44 -06:00
Krzysztof Parzyszek
7c9afe9183 [Hexagon] Fix gcc6 compilation issue 2020-12-10 08:17:07 -06:00
Benjamin Kramer
eeb713bbe2 [Hexagon] Fold single-use variables into assert. NFCI.
Silences unused variable warnings in Release builds.
2020-12-10 10:53:56 +01:00
Krzysztof Parzyszek
e3b2828b9d [Hexagon] Silence warnings about unused objects 2020-12-09 17:54:10 -06:00
Krzysztof Parzyszek
43d1c7a564 [Hexagon] Fix build: move template specialization into namespace scope 2020-12-09 17:40:15 -06:00
Krzysztof Parzyszek
f5d07a05bb [Hexagon] Realign HVX vectors wherever possible
Introduce HexagonVectorCombine as a helper class for vector-related
optimizations.
2020-12-09 17:11:25 -06:00
Mircea Trofin
bab72dd5d5 [NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister.
Typing the API appropriately.

Differential Revision: https://reviews.llvm.org/D92341
2020-12-02 15:46:38 -08:00
Krzysztof Parzyszek
b7bde0e4f3 [Hexagon] Improve check for HVX types
Allow non-simple types, like <17 x i32> to be treated as HVX vector
types.
2020-11-27 13:33:10 -06:00
Simon Pilgrim
c4628460b7 [Hexagon] Add HVX support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns
Followup to D92112 now that I've learnt about HVX type splitting.

This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876.

Differential Revision: https://reviews.llvm.org/D92169
2020-11-27 15:46:11 +00:00