shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
380,258 Commits 1,713 Branches 298 Tags
Commit Graph

16 Commits

Author SHA1 Message Date
Mircea Trofin
b470630913 [NFC] Removed unused prefixes from CodeGen/AMDGPU 
All the 'l'-starting tests.

Differential Revision: https://reviews.llvm.org/D94151
 2021-01-06 09:34:11 -08:00
Matt Arsenault
51a05d72ae AMDGPU: Drop remnants of byval support for shaders 
Before 2018, mesa used to use byval interchangably with inreg, which
didn't really make sense. Fix tests still using it to avoid breaking
in a future commit.

llvm-svn: 365953
 2019-07-12 20:12:17 +00:00
Matt Arsenault
72d27f5525 AMDGPU: Fix tests using old number for constant address space 
llvm-svn: 341770
 2018-09-10 02:54:25 +00:00
Joel E. Denny
9fa9c9368d [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 
See https://reviews.llvm.org/D47106 for details.

Reviewed By: probinson

Differential Revision: https://reviews.llvm.org/D47171

This commit drops that patch's changes to:

  llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
  llvm/test/CodeGen/NVPTX/param-load-store.ll

For some reason, the dos line endings there prevent me from commiting
via the monorepo.  A follow-up commit (not via the monorepo) will
finish the patch.

llvm-svn: 336843
 2018-07-11 20:25:49 +00:00
Dmitry Preobrazhensky
4c8f4234b6 [AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes 
See bug 36751: https://bugs.llvm.org/show_bug.cgi?id=36751

Differential Revision: https://reviews.llvm.org/D44529

Reviewers: artem.tamazov, arsenm
llvm-svn: 327723
 2018-03-16 16:38:04 +00:00
Nicolai Haehnle
770397f4cd AMDGPU: Do not combine loads/store across physreg defs 
Summary:
Since this pass operates on machine SSA form, this should only really
affect M0 in practice.

Fixes various piglit variable-indexing/vs-varying-array-mat4-index-*

Change-Id: Ib2a1dc3a8d7b08225a8da49a86f533faa0986aa8
Fixes: r317751 ("AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4")

Reviewers: arsenm, mareko, rampitec

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D40343

llvm-svn: 325677
 2018-02-21 13:31:35 +00:00
Matt Arsenault
1f17c66890 AMDGPU: Add cvt.pkrtz intrinsic 
Convert llvm.SI.packf16 test uses

llvm-svn: 295797
 2017-02-22 00:27:34 +00:00
Matt Arsenault
3ea06336fc AMDGPU: Remove some uses of llvm.SI.export in tests 
Merge some of the old, smaller tests into more complete versions.

llvm-svn: 295792
 2017-02-22 00:02:21 +00:00
Matt Arsenault
d2c8a337aa AMDGPU: Remove SI_fs_constant and SI_fs_interp intrinsics 
Update test uses with expansion in terms of new intrinsics.

llvm-svn: 295269
 2017-02-16 02:01:13 +00:00
Matt Arsenault
ebfba7027e AMDGPU: Change vintrp printing 
llvm-svn: 289664
 2016-12-14 16:36:12 +00:00
Matt Arsenault
618b330dd0 AMDGPU: Change vintrp printing to better match sc 
Some of the immediates need to be printed differently
eventually.

llvm-svn: 289291
 2016-12-10 00:23:12 +00:00
Tom Stellard
2a48433fcf AMDGPU/SI: Don't mark VINTRP instructions as mayLoad 
Summary:
These instructions technically do read from memory, but the memory
is considered to be out of bounds for normal load/store instructions.

shader-db stats:

SGPRS: 1416075 -> 1413323 (-0.19 %)
VGPRS: 867413 -> 863935 (-0.40 %)
Spilled SGPRs: 1409 -> 1354 (-3.90 %)
Spilled VGPRs: 63 -> 63 (0.00 %)
Private memory VGPRs: 880 -> 880 (0.00 %)
Scratch size: 2648 -> 2632 (-0.60 %) dwords per thread
Code Size: 37889052 -> 37897340 (0.02 %) bytes
LDS: 2147 -> 2147 (0.00 %) blocks
Max Waves: 279243 -> 280369 (0.40 %)
Wait states: 0 -> 0 (0.00 %)

Reviewers: nhaehnle, mareko, arsenm

Subscribers: kzhuravl, wdng, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D27593

llvm-svn: 289219
 2016-12-09 15:57:15 +00:00
Tom Stellard
2187bb8a89 AMDGPU: Add llvm.amdgcn.interp.mov intrinsic 
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D26725

llvm-svn: 288865
 2016-12-06 23:52:13 +00:00
Tom Stellard
1473f07ceb AMDGPU/SI: Use float as the operand type for amdgcn.interp intrinsics 
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye

Differential Revision: https://reviews.llvm.org/D26724

llvm-svn: 287962
 2016-11-26 02:26:04 +00:00
Nicolai Haehnle
df3a20cd80 AMDGPU: Add a shader calling convention 
This makes it possible to distinguish between mesa shaders
and other kernels even in the presence of compute shaders.

Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

Differential Revision: http://reviews.llvm.org/D18559

llvm-svn: 265589
 2016-04-06 19:40:20 +00:00
Tom Stellard
ad7d03daa6 AMDGPU/SI: Add llvm.amdgcn.v.interp.p[12] intrinsics 
Summary:
These are meant to be used instead of the llvm.SI.fs.interp intrinsic which
will be deprecated at some point.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15474

llvm-svn: 255651
 2015-12-15 17:02:49 +00:00