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4 Commits

Author SHA1 Message Date
Francis Visoiu Mistrih
c71cced0aa [CodeGen] Always use printReg to print registers in both MIR and debug 
output

As part of the unification of the debug format and the MIR format,
always use `printReg` to print all kinds of registers.

Updated the tests using '_' instead of '%noreg' until we decide which
one we want to be the default one.

Differential Revision: https://reviews.llvm.org/D40421

llvm-svn: 319445
 2017-11-30 16:12:24 +00:00
Colin LeMahieu
be8c453d58 [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing. 
llvm-svn: 239161
 2015-06-05 16:00:11 +00:00
Colin LeMahieu
c40be85adc Revert r239095 incorrect test tree. 
llvm-svn: 239102
 2015-06-04 21:32:42 +00:00
Colin LeMahieu
fc52c11d80 [Hexagon] Adding functionality for duplexing. Duplexing is a way to compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements. 
llvm-svn: 239095
 2015-06-04 21:16:16 +00:00