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Author	SHA1	Message	Date
Kang Zhang	513976df2e	[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118	2020-04-16 16:22:43 +00:00
Amy Kwan	d1dded28da	[PowerPC] Spill CR LT bits on P9 using setb This patch aims to spill CR[0-7]LT bits on POWER9 using the setb instruction. The sequence on P9 to spill these bits will be: setb %reg, %CRREG stw %reg, $FI Instead of the typical sequence: mfocrf %reg, %CRREG rlwinm %reg1, %reg, $SH, 0, 0 stw %reg1, $FI Differential Revision: https://reviews.llvm.org/D68443	2019-11-24 00:27:40 -06:00

Author

SHA1

Message

Date

Kang Zhang

513976df2e

[PowerPC] Ignore implicit register operands for MCInst

Summary:
When doing the conversion: MachineInst -> MCInst, we should ignore the
implicit operands, it will expose more opportunity for InstiAlias.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D77118

2020-04-16 16:22:43 +00:00

Amy Kwan

d1dded28da

[PowerPC] Spill CR LT bits on P9 using setb

This patch aims to spill CR[0-7]LT bits on POWER9 using the setb instruction.
The sequence on P9 to spill these bits will be:

setb %reg, %CRREG
stw %reg, $FI

Instead of the typical sequence:

mfocrf %reg, %CRREG
rlwinm %reg1, %reg, $SH, 0, 0
stw %reg1, $FI

Differential Revision: https://reviews.llvm.org/D68443

2019-11-24 00:27:40 -06:00

2 Commits