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Author	SHA1	Message	Date
Hsiangkai Wang	6e360460f1	[RISCV] Use v8-v23 as argument registers to conform to the proposal. The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171 Differential Revision: https://reviews.llvm.org/D95134	2021-01-22 07:55:24 +08:00
Fraser Cormack	c9154e8fa3	[RISCV] Add vector mask arithmetic ISel patterns The patterns that want to use 'vnot' use a custom PatFrag. This is because 'vnot' uses immAllOnesV which implicitly uses BUILD_VECTOR rather than SPLAT_VECTOR. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D94078	2021-01-07 09:43:25 +00:00

Author

SHA1

Message

Date

Hsiangkai Wang

6e360460f1

[RISCV] Use v8-v23 as argument registers to conform to the proposal.

The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171

Differential Revision: https://reviews.llvm.org/D95134

2021-01-22 07:55:24 +08:00

Fraser Cormack

c9154e8fa3

[RISCV] Add vector mask arithmetic ISel patterns

The patterns that want to use 'vnot' use a custom PatFrag. This is
because 'vnot' uses immAllOnesV which implicitly uses BUILD_VECTOR
rather than SPLAT_VECTOR.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94078

2021-01-07 09:43:25 +00:00

2 Commits