8108 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin
a8d9d50762 [AMDGPU] gfx90a support
Differential Revision: https://reviews.llvm.org/D96906
2021-02-17 16:01:32 -08:00
Fangrui Song
962b29d716 ELFObjectWriter: Don't sort non-local symbols
As we don't sort local symbols, don't sort non-local symbols.  This makes
non-local symbols appear in their register order, which matches GNU as. The
register order is nice in that you can write tests with interleaved CHECK
prefixes, e.g.

```
// CHECK: something about foo
.globl foo
foo:
// CHECK: something about bar
.globl bar
bar:
```

With the lexicographical order, the user needs to place lexicographical smallest
symbol first or keep CHECK prefixes in one place.
2021-02-13 10:32:27 -08:00
Fangrui Song
1f69355802 [test] Make ELF tests amenable to the order of non-local symbols 2021-02-12 21:00:42 -08:00
Stanislav Mekhanoshin
c0d7a8bc62 [AMDGPU] Allow accvgpr_read/write decode with opsel
These two instructions are VOP3P and have op_sel_hi bits,
however do not use op_sel_hi. That is recommended to set
unused op_sel_hi bits to 1. However, we cannot decode
both representations with 1 and 0 if bits are set to
default value 1. If bits are set to be ignored with '?'
initializer then encoding defaults them to 0.

The patch is a hack to force ignored '?' bits to 1 on
encoding for these instructions.

There is still canonicalization happens on disasm print
if incoming values are non-default, so that disasm output
does not match binary input, but this is pre-existing
problem for all instructions with '?' bits.

Fixes: SWDEV-272540

Differential Revision: https://reviews.llvm.org/D96543
2021-02-12 10:04:47 -08:00
luxufan
feaf1d81e3 [RISCV] Change parseVTypeI function
Change parseVTypeI function to Make the added vset instruction test cases report more concrete error message.

Differential Revision: https://reviews.llvm.org/D96218
2021-02-12 19:38:34 +08:00
Sander de Smalen
3b4f706ae1 [AArch64][SVE] Asm: Fix supported immediates for DUP/CPY
This patch fixes an issue in the implementation of DUP/CPY where certain
immediates were not accepted. Immediates should be interpreted as a two's
complement encoding of a value that fits the number of bits of the element
type.

          mov z0.b, p0/z, #127
     <=>  mov z0.b, p0/z, #-129
     <=>  mov z0.b, p0/z, #0xffffffffffffff7f

This behaviour is in line with the GNU assembler.

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D94776
2021-02-11 08:14:15 +00:00
Carl Ritson
e5b0b434f6 [AMDGPU] Refactor MIMG tables to better handle hardware variants
Add mimgopc object to represent the opcode allowing different
opcodes for different hardware variants.
This enables image_atomic_fcmpswap, image_atomic_fmin, and
image_atomic_fmax on GFX10

Reviewed By: foad, rampitec

Differential Revision: https://reviews.llvm.org/D96309
2021-02-11 13:22:41 +09:00
Nick Desaulniers
68945a8686 [Thumb2] support movs pc, lr alias for subs pc, lr, #0/eret
This is used by the Linux kernel built with CONFIG_THUMB2_KERNEL.

Because different operands are not permitted to `movs`, the diagnostics now provide multiple suggestions along the lines of using a non-pc destination operand or lr source operand.

Forked from D95586.

Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D96304
2021-02-10 11:00:42 -08:00
Daniel Cederman
ad3b023c88 [Sparc] Support relocatable expressions in the assembler
Allow assembler expressions to start with an identifier. This allows for expressions such as
```
b symbol + 4
```
and
```
mov symEnd - symStart, %g1
```

The patch builds upon https://reviews.llvm.org/D47136.

Reviewed By: joerg

Differential Revision: https://reviews.llvm.org/D47458
2021-02-10 14:52:44 +01:00
Sam Clegg
7e7cfce0b6 [WebAssembly] Use data sections by default
This allows data sections that don't start with `.data` to be
used/created.

Without this, clang's `__attribute__((section("foo")))` would
generate assembly that would not parse.

Differential Revision: https://reviews.llvm.org/D96233
2021-02-09 11:03:06 -08:00
Craig Topper
fd5adae02c [RISCV] Remove SRO* and SLO* instructions from bitmanip.
As of the current draft these are no longer being considered
for the bitmanip spec. It wasn't clear what sub extension they
belonged in in the 0.93 spec.

So remove them. They can always be added back if something changes.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96157
2021-02-09 09:35:05 -08:00
Dylan McKay
2ccb941740 [AVR] Fix global references to function symbols
References to functions are in program memory and need a `pm()` fixup. This should fix trait objects for Rust on AVR.

Differential Revision: https://reviews.llvm.org/D87631

Patch by Alex Mikhalev.
2021-02-10 00:40:49 +13:00
Hsiangkai Wang
a2d19bad07 [RISCV] Use whole register load/store for generic load/store.
In vector v0.10, there are whole vector register load/store
instructions. I suggest to use the whole register load/store
instructions for generic load/store for scalable vector types. It could
save up vset{i}vl{i} for these load/store.

For fractional LMUL, I keep to use vle{eew}.v/vse{eew}.v instructions to
load/store partial vector registers.

Differential Revision: https://reviews.llvm.org/D95853
2021-02-09 15:52:04 +08:00
Sam Clegg
01a48535c3 [MC][WebAssembly] Fix provisional values for data alias relocations
When calculating the symbol offsets to write as provisitonal values
in object files we are only interested in the offset of the symbol
itself.  For aliases this offset already includes the offset of the
base symbol.

The testin question was added back in https://reviews.llvm.org/D87407
but I believe the expectations here were incorrect.   sym_a lives
at offset 4 and sym_b lives 4 bytes into that (should be 8).

The addresses of the 3 symbosl in this object file are:

foo  : 0
sym_a: 4
sym_b: 8

Differential Revision: https://reviews.llvm.org/D96234
2021-02-08 16:56:57 -08:00
LemonBoy
45e33e8ba9 [SPARC] Recognize and handle the %lm(sym) operator
Reviewed By: joerg

Differential Revision: https://reviews.llvm.org/D77737
2021-02-08 19:25:33 -05:00
Martin Storsjö
71c29b4cf3 [AArch64] Use '//' as comment string for MSVC assembly
As the actual MSVC toolset doesn't use the GAS-style assembly that
Clang/LLVM produces and consumes, there's no reference for what
string to use for e.g. comments when building with a MSVC triple.

This frees up the use of semicolon as separator string, just like
was done for GNU targets in 23413195649d0cf6f3860ae8b5fb115b35032075.
(Previously, both the separator and comment strings were set to
the same, a semicolon.)

Compiler-rt extensively uses separator chars in its assembly,
and that assembly should be buildable with clang-cl for MSVC too.

Differential Revision: https://reviews.llvm.org/D96259
2021-02-08 22:30:14 +02:00
Dmitry Preobrazhensky
05433a8d03 [AMDGPU][MC] Corrected error position for invalid dim modifiers
Fixed bug 49054.

Differential Revision: https://reviews.llvm.org/D96117
2021-02-08 14:32:28 +03:00
Dmitry Preobrazhensky
168ccc8ecb [AMDGPU][MC][GFX10] Improved errors reporting for invalid MIMG NSA operands
Differential Revision: https://reviews.llvm.org/D96118
2021-02-08 14:04:28 +03:00
Fangrui Song
d3e13b58cd ELFObjectWriter: Don't de-duplicate STT_FILE symbols 2021-02-07 18:21:36 -08:00
Fangrui Song
09294642be ELFObjectWriter: Make STT_FILE precede associated local symbols 2021-02-07 17:51:40 -08:00
Fangrui Song
6042009633 [MC][test] Improve STT_FILE tests 2021-02-07 17:39:48 -08:00
Fangrui Song
980d28d955 ELFObjectWriter: Don't sort local symbols
GNU as does not sort local symbols. This has several advantages:

* The .symtab order is roughly the symbol occurrence order.
* The closest preceding STT_SECTION symbol is the definition of a local symbol.
* The closest preceding STT_FILE symbol is the defining file of a local symbol, if there are multiple default-version .file directives. (Not implemented in MC.)
2021-02-07 15:47:10 -08:00
Heejin Ahn
5afdd64a53 [WebAssembly] Update InstPrinter and AsmParser for new EH instructions
This updates InstPrinter and AsmParser for `delegate` and `catch_all`
instructions. Both will reject programs with multiple `catch_all`s per a
single `try`. And InstPrinter uses `EHInstStack` to figure out whether
to print catch label comments: It does not print catch label comments
for second `catch` or `catch_all` in a `try`.

Reviewed By: aardappel

Differential Revision: https://reviews.llvm.org/D94051
2021-02-06 08:54:56 -08:00
Joerg Sonnenberger
9179764710 SPARCv9: recognize SIR trap instruction 2021-02-06 01:34:02 +01:00
Wouter van Oortmerssen
a872ee2f36 [WebAssembly] ensure .functype applies to right label in assembler
We used to require .functype immediately follows the label it sets the type of, but not all Clang output follows this rule.

Now we simply allow it on any symbol, but only assume its a function start for a defined symbol, which is simpler and more general.

Fixes (part of) https://bugs.llvm.org/show_bug.cgi?id=49036

Differential Revision: https://reviews.llvm.org/D96165
2021-02-05 15:36:15 -08:00
Wouter van Oortmerssen
5e5b2cb131 [WebAssembly] Prevent data inside text sections in assembly
This is not supported in Wasm, unless the data was encoded instructions, but that wouldn't work with the assembler's other functionality (enforcing nesting etc.).

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48971

Differential Revision: https://reviews.llvm.org/D95838
2021-02-05 13:48:25 -08:00
Wouter van Oortmerssen
e3c0b0fe09 [WebAssembly] locals can now be indirect in DWARF
This for example to indicate that byval args are represented by a pointer to a struct.
Followup to https://reviews.llvm.org/D94140

Differential Revision: https://reviews.llvm.org/D94347
2021-02-05 11:14:42 -08:00
Hsiangkai Wang
c7189ba785 [RISCV] Add new vector instructions in v0.10.
* Add new vector instructions in v0.10.
 - load/store for mask value vle1.v vse1.v
 - vsetivli for 0-31 immediate vector length.
* Rename vector instructions in v0.10.
 - vfrsqrte7 -> vfrsqrt7
 - vfrece7 -> vfrec7
* Reserve memory width encodings for EEW>128b.

Differential Revision: https://reviews.llvm.org/D95781
2021-02-03 13:28:58 +08:00
Fangrui Song
3e8ab54ba0 [MC] Upgrade DWARF version to 5 upon .file 0
Without `-dwarf-version`, llvm-mc uses the default `MCContext::DwarfVersion` 4.

Without `-gdwarf-N`, Clang cc1as uses `clang::driver::ToolChain::GetDefaultDwarfVersion`
which is 4 on many toolchains. Note: `clang -c` can synthesize .debug_info without -g.

There is currently a MCParser warning upon `.file 0` and MCParser errors upon
`.loc 0` if the DWARF version is less than 5. This causes friction to the
following usage:

```
clang -S -g -gdwarf-5 a.c

// MC warning due to .file 0, MC error due to .loc 0
clang -c a.s
llvm-mc -filetype=obj a.s
```

My idea is that we can just upgrade `MCContext::DwarfVersion` to 5 upon
`.file 0` to make the above commands work.

The downside is that for an explicit version `clang -c -gdwarf-4 a.s`, it can be
argued that the new behavior drops the probably intended diagnostic. I think the
downside is small because in most cases DWARF version for an assembly action
should either match the original compile action or be omitted.

Ongoing discussion taking a similar action for GNU as: https://sourceware.org/pipermail/binutils/2021-January/114980.html

Differential Revision: https://reviews.llvm.org/D94882
2021-02-02 09:41:05 -08:00
Fangrui Song
1477ed8465 [MC] Support SHF_GNU_RETAIN as section flag 'R'
On Linux target triples, GNU as sets EI_OSABI to ELFOSABI_GNU when SHF_GNU_RETAIN is used。
On `*-*-freebsd`, it usually sets EI_OSABI to ELFOSABI_FREEBSD.

GNU ld respects SHF_GNU_RETAIN only for ELFOSABI_FREEBSD/ELFOSABI_GNU.
https://sourceware.org/bugzilla/show_bug.cgi?id=27282

MC doesn't set ELFOSABI_GNU for SHF_GNU_RETAIN/STB_GNU_UNIQUE/STT_GNU_IFUNC.
MC assembled object files do not have special semantics in GNU ld.

Reviewed By: psmith

Differential Revision: https://reviews.llvm.org/D95730
2021-02-02 09:34:09 -08:00
Dmitry Preobrazhensky
586df38478 [AMDGPU][MC] Corrected parsing of optional modifiers
Fixed bugs in parsing of "no*" modifiers and improved errors handling.
See https://bugs.llvm.org/show_bug.cgi?id=41282.

Differential Revision: https://reviews.llvm.org/D95675
2021-02-02 14:52:29 +03:00
Andrew Ng
94fedd2661 [X86] Fix disassembly of x86-64 GDTLS code sequence
For x86-64 the REX.w prefix takes precedence over any other size
override (i.e. 0x66). Therefore, for x86-64 when REX.w is present set
'hasOpSize' to false to ensure that any size override is ignored.

Fixes PR48901.

Differential Revision: https://reviews.llvm.org/D95682
2021-02-02 11:35:00 +00:00
Simon Pilgrim
4d904776a7 [X86][AVX] Add missing VEX_WIG tags from VPACKUSDW/VPHSUBD/VPCMPISTRI/VPCMPISTRM/VPCMPESTRI/VPCMPESTRM
Fixes PR48877

Differential Revision: https://reviews.llvm.org/D95801
2021-02-02 11:25:44 +00:00
Wouter van Oortmerssen
0d9b17d0ef [WebAssembly] fixed wasm64 data segment init exp not 64-bit
As defined in the spec:
https://github.com/WebAssembly/memory64/blob/master/proposals/memory64/Overview.md

Differential Revision: https://reviews.llvm.org/D95651
2021-02-01 11:32:50 -08:00
Craig Topper
c691fe14da [X86] Accept 64-bit GPRs for vextractps when using a register that requires EVEX.
This is consistent with the VEX version. It also fixes a sorting
issue in the matching table that caused the EVEX version to be
prioritized over VEX in intel syntax.

Fixes issue [2] from PR48991.
2021-02-01 11:01:32 -08:00
Simon Pilgrim
e9514429a0 [X86][AVX] Add 'OK' tests cases for PR48877 2021-02-01 18:17:41 +00:00
Dmitry Preobrazhensky
99b5631649 [AMDGPU][MC] Corrected error position for invalid operands
Generic parser may report an incorrect error position when an offending operand is followed by a comma.
See bug 48884 for details: https://bugs.llvm.org/show_bug.cgi?id=48884.

Differential Revision: https://reviews.llvm.org/D95674
2021-02-01 14:31:08 +03:00
Hsiangkai Wang
282aca10ae [RISCV] Update the version number to v0.10 for vector.
v0.10 is tagged in V specification. Update the version to v0.10.

Differential Revision: https://reviews.llvm.org/D95680
2021-01-30 07:20:05 +08:00
Jay Foad
164c6de530 [AMDGPU] Test all register names known to AMDGPUPALMetadata
Differential Revision: https://reviews.llvm.org/D95684
2021-01-29 16:16:26 +00:00
Abhina Sreeskantharajan
42a21778f6 [test] Use host platform specific error message substitution in lit tests
On z/OS, the following error message is not matched correctly in lit tests.

```
EDC5129I No such file or directory.
```

This patch uses a lit config substitution to check for platform specific error messages.

Reviewed By: muiez, jhenderson

Differential Revision: https://reviews.llvm.org/D95246
2021-01-29 07:16:30 -05:00
Thomas Lively
4b68b64dcc [WebAssembly] Prototype i8x16 to i32x4 widening instructions
As proposed in https://github.com/WebAssembly/simd/pull/395 and matching the
opcodes used in V8:
https://chromium-review.googlesource.com/c/v8/v8/+/2617385/4/src/wasm/wasm-opcodes.h

Differential Revision: https://reviews.llvm.org/D95557
2021-01-28 10:59:32 -08:00
Tobias Burnus
70ea15b889 [MC][ELF] Fix accepting abbreviated form with sh_flags and sh_entsize
Followup to D92052 as I missed an issue as shown via GCC bug https://gcc.gnu.org/PR97827, namely: (e.g.) ".rodata." implies ELF::SHF_ALLOC.

Crossref:

- D73999 / commit 75af9da755721123e62b45cd0bc0c5e688a9722a
  added for LLVM 11 a check that sh_flags and sh_entsize (and sh_type)
  changes are an error, in line with GNU assembler.

-  D92052 / commit 1deff4009e0ae661b03682901bf6932297ce7ea1
   permitted the abbreviated form which many assemblers accept and
   GCC generates: while the first .section contains the flags and entsize,
   subsequent sections simply contain the name without repeating entsize or
   flags.

However, the latter patch missed in the check that some flags are automatically set, e.g. '.rodata." implies ELF::SHF_ALLOC.

Related https://bugs.llvm.org/show_bug.cgi?id=48201

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D94072
2021-01-28 14:54:43 +00:00
Craig Topper
e1d6178951 [RISCV] Add rv64 run lines to rv32 MC layer tests for B extension
Remove common instructions from rv64 tests since they are now
covered by the rv64 run lines in the rv32 tests.

Add rv32-only* tests for a few cases that aren't common between
r32 and rv64.

Addresses review feedback from D95150.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D95272
2021-01-26 17:20:05 -08:00
Austin Kerbow
2291bd137d [AMDGPU] Update subtarget features for new target ID support
Support for XNACK and SRAMECC is not static on some GPUs. We must be able
to differentiate between different scenarios for these dynamic subtarget
features.

The possible settings are:

- Unsupported: The GPU has no support for XNACK/SRAMECC.
- Any: Preference is unspecified. Use conservative settings that can run anywhere.
- Off: Request support for XNACK/SRAMECC Off
- On: Request support for XNACK/SRAMECC On

GCNSubtarget will track the four options based on the following criteria. If
the subtarget does not support XNACK/SRAMECC we say the setting is
"Unsupported". If no subtarget features for XNACK/SRAMECC are requested we
must support "Any" mode. If the subtarget features XNACK/SRAMECC exist in the
feature string when initializing the subtarget, the settings are "On/Off".

The defaults are updated to be conservatively correct, meaning if no setting
for XNACK or SRAMECC is explicitly requested, defaults will be used which
generate code that can be run anywhere. This corresponds to the "Any" setting.

Differential Revision: https://reviews.llvm.org/D85882
2021-01-26 11:25:51 -08:00
Dmitry Preobrazhensky
745064e36b [AMDGPU][MC] Refactored exp tgt handling
Summary:
- Separated tgt encoding from parsing;
- Separated tgt decoding from printing;
- Improved errors handling;
- Disabled leading zeroes in index. The following code is no longer accepted: exp pos00 v3, v2, v1, v0

Reviewers: arsenm, rampitec, foad

Differential Revision: https://reviews.llvm.org/D95216
2021-01-26 14:54:15 +03:00
Sam Clegg
d705c2fbd4 Revert "[WebAssembly] MC layer writes table symbols to object files"
This reverts commit d806618636f8a82bfc3f620e1fad83af4d2a2575.
Review: https://reviews.llvm.org/D92215

We had issues where older versions of wasm-ld were crashing on object
files containing a table symbol.  We decided that the best strategy
going forward is to only generate these symbol if refernece types is
enabled.  Without reference types enabled we should never geneate a
table symbol or a TABLE_NUMBER relocation.

This revert is in addition to the one already reverted in
https://reviews.llvm.org/D95005.

The plan is to re-land these in updated form after the llvm 12 branch.

Differential Revision: https://reviews.llvm.org/D95420
2021-01-25 22:32:36 -08:00
Hsiangkai Wang
f19849a07b [RISCV] Update V extension to v1.0-draft 08a0b464.
Differential Revision: https://reviews.llvm.org/D94583
2021-01-26 12:02:43 +08:00
Dmitry Preobrazhensky
558b3bbb5b [AMDGPU][MC] Improved errors handling for SDWA operands
Reviewers: rampitec

Differential Revision: https://reviews.llvm.org/D95212
2021-01-25 19:02:53 +03:00
Simon Cook
a7c1239f37 [RISCV] Add attribute support for all supported extensions
This adds support for ".attribute arch" for all extensions that are
currently supported by the compiler.

Differential Revision: https://reviews.llvm.org/D94931
2021-01-25 08:58:53 +00:00
Craig Topper
607e5a5000 [RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32.
Add tests to make sure common instructions are accepted in RV64
and not just RV32.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D95150
2021-01-22 13:52:26 -08:00