806 Commits

Author SHA1 Message Date
Micah Weston
23faa81d3f
[SHT_LLVM_BB_ADDR_MAP] Avoids side-effects in addition since order is unspecified. (#79168)
Turns out the problem with
https://github.com/llvm/llvm-project/issues/60013 is due to the fact
that order of operation is unspecified in C++:
https://en.cppreference.com/w/cpp/language/eval_order. A small example
of where this manifests with MSVC can be seen here
https://ooo.godbolt.org/z/bxqKeqzqn.

This patch does the following:
* Removes the addition operations where we sequence more than one
side-effect based expression.
* Removes test guards to now run on Windows
2024-01-24 17:26:48 -05:00
Saiyedul Islam
33ec6b3de7
[AMDGPU] Update llvm-objdump lit tests for COV5 (#79039)
Depends on #79038 which makes cov5 as the default code
object version.
2024-01-23 17:08:38 +05:30
Micah Weston
99ffe71921 [llvm-objdump] Disables running pgo-analysis-map symbolizing on windows. 2024-01-19 20:40:17 -05:00
Aiden Grossman
f9bc1ee3fc
[llvm-objdump] Add support for symbolizing PGOBBAddrMap Info (#76386)
This patch adds in support for symbolizing PGO information contained
within the SHT_LLVM_BB_ADDR_MAP section in llvm-objdump. The outputs are
simply the raw values contained within the section.
2024-01-19 14:28:31 -08:00
Fangrui Song
9e9907f1cf
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
Similar to 806761a7629df268c8aed49657aeccffa6bca449.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
2024-01-16 21:54:58 -08:00
Derek Schuff
428cf71ffa Reland "[WebAssembly][Object]Use file offset as function symbol address for linked files (#76198)"
WebAssembly doesn't have a single virtual memory space the way other object
formats or architectures do, so "addresses" mean different things depending
on the context.
Function symbol addresses in object files are offsets from the start of the code
section. This is good for linking and relocation. However when dealing with
linked binaries, offsets from the start of the file/module are more often
used (e.g. for stack traces in browsers), and are more useful for use
cases like binary size attribution. This PR changes Object to use
the file offset instead of the section offset for function symbols, but
only for linked (non-DSO) files.

This is a reland of fc5f51cf with a fix for the MSan failure (it was not caused
by this change, but it was revealed by the new tests).
2024-01-03 15:39:48 -08:00
Mitch Phillips
665d1a0eb4 Revert "[WebAssembly][Object]Use file offset as function symbol address for linked files (#76198)"
This reverts commit fc5f51cf5af4364b38bf22e491d46e1e892ade0c.

Reason: Broke the sanitizer buildbot -
https://lab.llvm.org/buildbot/#/builders/5/builds/39751/steps/12/logs/stdio
2024-01-03 11:23:10 +01:00
Derek Schuff
fc5f51cf5a
[WebAssembly][Object]Use file offset as function symbol address for linked files (#76198)
WebAssembly doesn't have a single virtual memory space the way other
object formats or architectures do, so "addresses" mean different things
depending on the context.
Function symbol addresses in object files are offsets from the start of
the code section. This is good for linking and relocation. However when
dealing with linked binaries, offsets from the start of the file/module
are more often used (e.g. for stack traces in browsers), and are more
useful for use cases like binary size attribution. This PR changes
Object to use the file offset instead of the section offset for function
symbols, but only for linked (non-DSO) files.

This implements item number 4 from #76107
2024-01-02 14:54:54 -08:00
Jay Foad
c01e844a7e
[AMDGPU] Update compute program resource registers for GFX12 (#75911)
Co-authored-by: Konstantin Zhuravlyov <kzhuravl@amd.com>
2024-01-02 13:24:42 +00:00
stephenpeckham
7026086073
[XCOFF] Use RLDs to print branches even without -r (#74342)
This presents misleading and confusing output. If you have a function
defined at the beginning of an XCOFF object file, and you have a
function call to an external function, the function call disassembles as
a branch to the local function. That is,

`void f() { f(); g();}`

disassembles as 
>00000000 <.f>:
       0: 7c 08 02 a6   mflr 0
4: 94 21 ff c0 stwu 1, -64(1)
       8: 90 01 00 48   stw 0, 72(1)
      c: 4b ff ff f5   bl 0x0 <.f>
      10: 4b ff ff f1   bl 0x0 <.f> 

With this PR, the second call will display:

`10: 4b ff ff f1   bl 0x0 <.g>  `

Using -r can help, but you still get the confusing output:

>10: 4b ff ff f1   bl 0x0 <.f>
      00000010:  R_RBR        .g
2023-12-21 08:17:32 -06:00
Sam Clegg
4e8cb01b01
[WebAssembly] Add symbol information for shared libraries (#75238)
The current (experimental) spec for WebAssembly shared libraries does
not include a full symbol table like the object format. This change
extracts symbol information from the normal wasm exports.

This is the first step in having the linker report undefined symbols
when linking with shared libraries. The current behaviour is to ignore
all undefined symbols when linking with `-pie` or `-shared`.

See https://github.com/emscripten-core/emscripten/issues/18198
2023-12-20 11:13:09 -08:00
Fangrui Song
3cd1e73909
[llvm-objdump] Add -mllvm (#75892)
When llvm-objdump switched from cl:: to OptTable
(https://reviews.llvm.org/D100433), we dropped support for LLVM cl::
options. Some LLVM_DEBUG in `llvm/lib/Target/$target/MCDisassembler/`
files might be useful. Add -mllvm to allow dumping the information.

```
# -debug is available in an LLVM_ENABLE_ASSERTIONS=on build
llvm-objdump -d -mllvm -debug a.o > /dev/null
```

Link:
https://discourse.llvm.org/t/how-to-enable-debug-logs-in-llvm-objdump/75758
2023-12-19 00:52:39 -08:00
Fangrui Song
644e6d7d8b
[llvm-objdump] --disassemble-symbols: skip inline relocs from symbols that are not dumped (#75724)
When a section contains two functions x1 and x2, we incorrectly display
x1's relocations when dumping x2 for `--disassemble-symbols=x2 -r`.
Fix #75539 by ignoring these relocations.
2023-12-18 09:53:44 -08:00
Fangrui Song
942b0901b0 [llvm-objdump,test] Improve zero dumping and inline relocs tests 2023-12-16 16:54:45 -08:00
Fangrui Song
0ca95b269f [llvm-objdump,test] Improve zero dumping and inline relocs tests 2023-12-16 15:43:41 -08:00
Wang Yaduo
c532ba4edd [RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-hex flag.
2023-12-14 22:42:11 -08:00
Vitaly Buka
fc3adf74d3
Revert "[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format" (#75561)
Reverts llvm/llvm-project#74053

Breaks https://lab.llvm.org/buildbot/#/builders/5/builds/39291

Co-authored-by: Wang Yaduo <wangyaduo@linux.alibaba.com>

Issue #75563
2023-12-14 22:05:47 -08:00
Wang Yaduo
3dde0d0256
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-hex flag.
2023-12-15 10:13:20 +08:00
stephenpeckham
2fd7657b66
[XCOFF] Display branch-absolute targets in hex. (#72532)
Branch-absolute instructions are currently printed in decimal, and
negative addresses are printed as positive numbers.

With this change, addresses are printed in hex and negative addresses
are converted to an unsigned 32- or 64-bit address.
2023-12-13 12:55:47 -06:00
Daniil Kovalev
f0c0116c48
[test][llvm-objdump][AArch64] Add tests for ELF AUTH constants (#74298)
This patch introduces llvm-objdump tests for new `AARCH64_AUTH_RELR`,
`AARCH64_AUTH_RELRSZ` and `AARCH64_AUTH_RELRENT` dynamic tags.

Depends on https://github.com/llvm/llvm-project/pull/74874
2023-12-09 23:51:59 +03:00
Jason Liu
623cd75105
[llvm-objdump] Fix lma display issue for non-bss sections (#72141)
llvm-readobj and llvm-objdump have inconsistent handling of display
lma for sections.
This patch tries to common code up and adapt the same approach for
both tools.
2023-11-27 12:24:39 -05:00
Chen Zheng
abc405858d
[XCOFF] make related SD symbols as isFunction (#69553)
This will help tools like llvm-symbolizer recognizes more functions.
2023-11-26 11:59:09 +08:00
Jay Foad
cf1e0c0b07
[AMDGPU] Define new targets gfx1200 and gfx1201 (#73133)
Define target names and ELF numbers for new GFX12 targets gfx1200 and
gfx1201. For now they behave identically to GFX11.
2023-11-23 16:44:05 +00:00
ZhaoQi
1c68c4c57a
[LoongArch][MC] Modify branch evaluation for MCInstrAnalysis (#73205)
Function evaluateBranch() is used to compute target address for a given
branch instruction and return true on success. But target address of
indirect branch cannot be simply added, so rule it out and just return
false.

This patch also add objdump tests which capture the current state of
support for printing branch targets. Without this patch, the result of
"jirl $zero, $a0, 4" is "jirl $zero, $a0, 4 <foo+0x64>". It is obviously
incorrect, because this instruction represents an indirect branch whose
target address depends on both the register value and the imm. After
this patch, it will be right despite loss of details.
2023-11-23 16:38:41 +08:00
Job Noorman
95f924f30a
[RISCV][MC] Implement evaluateBranch for auipc+jalr pairs (#65480)
This patch implements `MCInstrAnalysis` state in order to be able
analyze auipc+jalr pairs inside `evaluateBranch`.

This is implemented as follows:
- State: array of currently known GPR values;
- Whenever an auipc is detected in `updateState`, update the state value
of RD with the immediate;
- Whenever a jalr is detected in `evaluateBranch`, check if the state
holds a value for RS1 and use that to compute its target.

Note that this is similar to how binutils implements it and the output
of llvm-objdump should now mostly match the one of GNU objdump.

This patch also updates the relevant llvm-objdump patches and adds a new
one testing the output for interleaved auipc+jalr pairs.
2023-10-20 06:36:12 +00:00
Konstantin Zhuravlyov
6cfb64276d
AMDGPU: Minor updates to program resource registers (#69525)
- Be explicit about which program resource register is supported by
which target
    - RSRC1
      - FP16_OVFL is GFX9+
      - WGP_MODE is GFX10+
      - MEM_ORDERED is GFX10+
      - FWD_PROGRESS is GFX10+
    - RSRC3
      - INST_PREF_SIZE is GFX11+
      - TRAP_ON_START is GFX11+
      - TRAP_ON_END is GFX11+
      - IMAGE_OP is GFX11+
  - Do not emit GFX11+ fields when disassembling GFX10 code objects
  - Tighten enforcement of reserved bits in disassembler

---------

Co-authored-by: Konstantin Zhuravlyov <kzhuravl@amd.com>
2023-10-19 12:40:19 -04:00
Frederic Cambus
a921f2a3d7
[llvm-objdump] Add support for the PT_OPENBSD_NOBTCFI segment type. (#67127)
Reference: https://github.com/openbsd/src/blob/master/sys/sys/exec_elf.h
2023-09-22 21:40:58 +02:00
Eduard Zingerman
d15f96fe4b [BPF][DebugInfo] Show CO-RE relocations in llvm-objdump
Extend llvm-objdump to show CO-RE relocations when `-r` option is
passed and object file has .BTF and .BTF.ext sections.

For example, the following C program:

    #define __pai __attribute__((preserve_access_index))

    struct foo { int i; int j;} __pai;
    struct bar { struct foo f[7]; } __pai;
    extern void sink(void *);

    void root(struct bar *bar) {
      sink(&bar[2].f[3].j);
    }

Should lead to the following objdump output:

    $ clang --target=bpf -O2 -g t.c -c -o - | \
        llvm-objdump  --no-addresses --no-show-raw-insn -dr -

    ...
            r2 = 0x94
                    CO-RE <byte_off> [2] struct bar::[2].f[3].j (2:0:3:1)
            r1 += r2
            call -0x1
                    R_BPF_64_32     sink
            exit
    ...

More examples could be found in unit tests, see BTFParserTest.cpp.

To achieve this:
- Move CO-RE relocation kinds definitions from BPFCORE.h to BTF.h.
- Extend BTF.h with types derived from BTF::CommonType, e.g.
  BTF::IntType and BTF::StrutType, to allow dyn_cast() and access to
  type additional data.
- Extend BTFParser to load BTF type and relocation data.
- Modify llvm-objdump.cpp to create instance of BTFParser when
  disassembly of object file with BTF sections is processed and `-r`
  flag is supplied.

Additional information about CO-RE is available at [1].

[1] https://docs.kernel.org/bpf/llvm_reloc.html

Depends on D149058

Differential Revision: https://reviews.llvm.org/D150079
2023-09-21 21:59:10 +03:00
Austin Kerbow
69447d6afe [AMDGPU] Add ASM and MC updates for preloading kernargs
Add assembler directives for preloading kernel arguments that correspond
to new fields in the kernel descriptor for the length and offset of
arguments that will be placed in SGPRs prior to kernel launch. Alignment
of the arguments in SGPRs is equivalent to the kernarg segment when
accessed via the kernarg_segment_ptr. Kernarg SGPRs are allocated
directly after other user SGPRs.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D159459
2023-09-19 15:45:16 -07:00
Guozhi Wei
cbdccb30c2 [RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
If a virtual register is not assigned preferred physical register, it means some
COPY instructions will be changed to real register move instructions. In this
case we can try to split the virtual register in colder blocks, if success, the
original COPY instructions can be deleted, and the new COPY instructions in
colder blocks will be generated as register move instructions. It results in
fewer dynamic register move instructions executed.

The new test case split-reg-with-hint.ll gives an example, the hot path contains
24 instructions without this patch, now it is only 4 instructions with this
patch.

Differential Revision: https://reviews.llvm.org/D156491
2023-09-15 19:52:50 +00:00
Saiyedul Islam
466a8149b3
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
This reverts commit 0a8d17e79b02a92814a2a788d79df1f54d70ec3e.
2023-09-12 15:13:59 +05:30
Saiyedul Islam
0a8d17e79b
[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)
Also update LIT tests and docs.
For more details, see
https://llvm.org/docs/AMDGPUUsage.html#code-object-v5-metadata

Reviewed By: arsenm, jhuber6

Github PR: #65410

Differential Revision: https://reviews.llvm.org/D129818
2023-09-12 13:53:31 +05:30
Shivam Gupta
7b7470600c [llvm-objdump] --adjust-vma adjust symbol table
Add a shouldAdjustVA(Section) guard on top of address update.

Update llvm-objdump file to update symbol table when --adjust-vma used.

Fixes #63203

Patch by HamidrezaSK (Hamidreza Sanaee)
2023-09-11 09:57:27 +05:30
Jonas Devlieghere
a23b9b7ef1
[llvm-objdump] Require AArch64 backed for arm64-disassembly-color
This test depends on the AArch64 backend.
2023-09-01 11:07:35 -07:00
Jonas Devlieghere
7678a32219
[llvm-objdump] Disable arm64-disassembly-color on Windows
Windows doesn't support colored output with ANSI escape colors.
2023-09-01 10:09:14 -07:00
Jonas Devlieghere
95062d7467
[llvm-objdump] Enable disassembly color highlighting
Enable color highlighting of disassembly in llvm-objdump. This patch
introduces a new flag --disassembler-color=<mode> that enables or
disables highlighting disassembly with ANSI escape codes. The default
mode is to enable color highlighting if outputting to a color-enabled
terminal.

Differential revision: https://reviews.llvm.org/D159224
2023-09-01 09:32:34 -07:00
David Spickett
40ee8abee7 [llvm-objdump] Make arm64ec.yaml warning check less strict to account for Windows
When 7a28b0b60e81a0472bfc6af992e824ef01cc08b8 added this it wanted
"llvm-objdump: warning: <...>". On our Windows on Arm bot you get:
c:\users\tcwg\llvm-worker\clang-arm64-windows-msvc\stage1\bin\llvm-objdump.exe: warning:

Seems unlikely the warning would come from anywhere else and if
it does, this test isn't the one to be catching that. So I've
shortened the checks to start at "warning: ".
2023-08-15 16:46:04 +00:00
Jacek Caban
7a28b0b60e [llvm-objdump] Support CHPE code ranges in disassembler.
Reviewed By: jhenderson, MaskRay
Differential Revision: https://reviews.llvm.org/D149095
2023-08-15 00:06:51 +02:00
Fangrui Song
099f4e236c [llvm-debuginfod] Switch to xxh3_64bits
Many sources show that xxh3 is much better than xxh64. This particular
instance may or may not have noticeable difference, but this change
moves us toward removing xxHash64.

This change will invalid cache.

Reviewed By: mysterymath

Differential Revision: https://reviews.llvm.org/D155993
2023-08-11 12:37:18 -07:00
Wael Yehia
9d4e8c09f4 [XCOFF] Do not put MergeableCStrings in their own section
The current implementation generates a csect with a
".rodata.str.x.y" prefix for a MergeableCString variable definition.
However, a reference to such variable does not get the prefix in its
name because there's not enough information in the containing IR.
In particular, without seeing the initializer and absent of some other
indicators, we cannot tell that the referenced variable is a null-
terminated string.

When the AIX codegen in llvm was being developed, the prefixing was copied
from ELF without having the linker take advantage of the info.
Currently, the AIX linker does not have the capability to merge
MergeableCString variables. If such feature would ever get implemented,
the contract between the linker and compiler would have to be reconsidered.

Here's the before and after of this change:
```
@a = global i64 320255973571806, align 8
@strA = unnamed_addr constant [7 x i8] c"hello\0A\00", align 1  ;; Mergeable1ByteCString
@strB = unnamed_addr constant [8 x i8] c"Blahah\0A\00", align 1 ;; Mergeable1ByteCString
@strC = unnamed_addr constant [2 x i16] [i16 1, i16 0], align 2 ;; Mergeable2ByteCString
@strD = unnamed_addr constant [2 x i16] [i16 1, i16 1], align 2 ;; !isMergeableCString
@strE = external unnamed_addr constant [2 x i16], align 2

-fdata-sections:
  .text  extern        .rodata.str1.1strA        .text  extern        strA
    0    SD       RO                               0    SD       RO
  .text  extern        .rodata.str1.1strB        .text  extern        strB
    0    SD       RO                               0    SD       RO
  .text  extern        .rodata.str2.2strC  ===>  .text  extern        strC
    0    SD       RO                               0    SD       RO
  .text  extern        strD                      .text  extern        strD
    0    SD       RO                               0    SD       RO
  .data  extern        a                         .data  extern        a
    0    SD       RW                               0    SD       RW
  undef  extern        strE                      undef  extern        strE
    0    ER       UA                               0    ER       UA

-fno-data-sections:
  .text  unamex        .rodata.str1.1            .text  unamex        .rodata
    0    SD       RO                               0    SD       RO
  .text  extern        strA                      .text  extern        strA
    0    LD       RO                               0    LD       RO
  .text  extern        strB                      .text  extern        strB
    0    LD       RO                               0    LD       RO
  .text  unamex        .rodata.str2.2      ===>  .text  extern        strC
    0    SD       RO                               0    LD       RO
  .text  extern        strC                      .text  extern        strD
    0    LD       RO                               0    LD       RO
  .text  unamex        .rodata                   .data  unamex        .data
    0    SD       RO                               0    SD       RW
  .text  extern        strD                      .data  extern        a
    0    LD       RO                               0    LD       RW
  .data  unamex        .data                     undef  extern        strE
    0    SD       RW                               0    ER       UA
  .data  extern        a
    0    LD       RW
  undef  extern        strE
    0    ER       UA
```

Reviewed by: David Tenty, Fangrui Song

Differential Revision: https://reviews.llvm.org/D156202
2023-07-29 03:24:21 +00:00
Fangrui Song
9ea44c6894 [llvm-objdump] -d: don't display mapping symbols as labels
Similar to D96617 for llvm-symbolizer.

This patch matches the GNU objdump -d behavior to suppress printing
labels for mapping symbols. Mapping symbol names don't convey much
information.

When --show-all-symbols (not in GNU) is specified, we still print
mapping symbols.

Note: the `for (size_t SI = 0, SE = Symbols.size(); SI != SE;)` loops
needs to iterate all mapping symbols, even if they are not displayed.
We use the new field `IsMappingSymbol` to recognize mapping symbols.
This field also enables simplification after D139131.

ELF/ARM/disassemble-all-mapping-symbols.s is enhanced to add `.space 2`.
If `End = std::min(End, Symbols[SI].Addr);` is not correctly set, we
would print a `.word`.

Reviewed By: jhenderson, jobnoorman, peter.smith

Differential Revision: https://reviews.llvm.org/D156190
2023-07-27 20:51:42 -07:00
Fangrui Song
bf5581dce6 [llvm-objdump][test] Improve elf-aarch64-mapping-symbols.test 2023-07-24 17:21:28 -07:00
Jacek Caban
23821568f6 [llvm-objdump] [NFC] Add missing REQUIRES to arm64ec.yaml.
Differential Revision: https://reviews.llvm.org/D149091
2023-07-24 20:56:54 +02:00
Jacek Caban
c33397f712 Recognize ARM64EC binaries in COFFObjectFile::getMachine.
ARM64EC/ARM64X binaries use ARM64 or AMD64 machine types, but provide
additional CHPE metadata that may be used to distinguish them from
pure ARM64/AMD64 binaries.

Reviewed By: jhenderson, MaskRay, mstorsjo
Differential Revision: https://reviews.llvm.org/D149091
2023-07-24 20:41:20 +02:00
Rahman Lavaee
bf98aaae00 [llvm-objdump] Use BBEntry::BBID to represent basic block numbers.
Reviewed By: aidengrossman, mtrofin, JestrTulip

Differential Revision: https://reviews.llvm.org/D155464
2023-07-21 11:45:31 -07:00
Jay Foad
92542f2a40 [AMDGPU] Add targets gfx1150 and gfx1151
This is the target definition only. Currently they are treated the same
as GFX 11.0.x.

Differential Revision: https://reviews.llvm.org/D155429
2023-07-17 13:06:12 +01:00
Stephen Peckham
ac5d5351d4 Use empty symbol name for XCOFF text csect
When generating XCOFF, the compiler generates a csect with an internal
name.  Each function results in a label within the csect.  This patch
replaces the internal name ".text" with an empty string "".  This avoids
adding special code to handle a function text() in the source file, and
works better with some XCOFF tools that are confused when the csect and
the first function have the same address.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D154854
2023-07-15 16:13:48 -04:00
Fangrui Song
a4d1259e61 [llvm-objdump] Default to --mcpu=future for PPC32
Extend D127824 to the 32-bit Power architecture.
AFAICT GNU objdump -d dumps all instructions for 32-bit as well.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D155114
2023-07-12 18:24:18 -07:00
Eduard Zingerman
c8e055d485 [BPF][DebugInfo] Use .BPF.ext for line info when DWARF is not available
"BTF" is a debug information format used by LLVM's BPF backend.
The format is much smaller in scope than DWARF, the following info is
available:
- full set of C types used in the binary file;
- types for global values;
- line number / line source code information .

BTF information is embedded in ELF as .BTF and .BTF.ext sections.
Detailed format description could be found as a part of Linux Source
tree, e.g. here: [1].

This commit modifies `llvm-objdump` utility to use line number
information provided by BTF if DWARF information is not available.
E.g., the goal is to make the following to print source code lines,
interleaved with disassembly:

    $ clang --target=bpf -g test.c -o test.o
    $ llvm-strip --strip-debug test.o
    $ llvm-objdump -Sd test.o

    test.o:	file format elf64-bpf

    Disassembly of section .text:

    <foo>:
    ; void foo(void) {
    	r1 = 0x1
    ;   consume(1);
    	call -0x1
    	r1 = 0x2
    ;   consume(2);
    	call -0x1
    ; }
    	exit

A common production use case for BPF programs is to:
- compile separate object files using clang with `-g -c` flags;
- link these files as a final "static" binary using bpftool linker ([2]).
The bpftool linker discards most of the DWARF sections
(line information sections as well) but merges .BTF and .BTF.ext sections.
Hence, having `llvm-objdump` capable to print source code using .BTF.ext
is valuable.

The commit consists of the following modifications:

- llvm/lib/DebugInfo/BTF aka `DebugInfoBTF` component is added to host
  the code needed to process BTF (with assumption that BTF support
  would be added to some other tools as well, e.g. `llvm-readelf`):
  - `DebugInfoBTF` provides `llvm::BTFParser` class, that loads information
    from `.BTF` and `.BTF.ext` sections of a given `object::ObjectFile`
    instance and allows to query this information.
    Currently only line number information is loaded.

  - `DebugInfoBTF` also provides `llvm::BTFContext` class, which is an
    implementation of `DIContext` interface, used by `llvm-objdump` to
    query information about line numbers corresponding to specific
    instructions.

- Structure `DILineInfo` is modified with field `LineSource`.

  `DIContext` interface uses `DILineInfo` structure to communicate
  line number and source code information.
  Specifically, `DILineInfo::Source` field encodes full file source code,
  if available. BTF only stores source code for selected lines of the
  file, not a complete source file. Moreover, stored lines are not
  guaranteed to be sorted in a specific order.

  To avoid reconstruction of a file source code from a set of
  available lines, this commit adds `LineSource` field instead.

- `Symbolize` class is modified to use `BTFContext` instead of
  `DWARFContext` when DWARF sections are not available but BTF
  sections are present in the object file.
  (`Symbolize` is instantiated by `llvm-objdump`).

- Integration and unit tests.

Note, that DWARF has a notion of "instruction sequence".
DWARF implementation of `DIContext::getLineInfoForAddress()` provides
inexact responses if exact address information is not available but
address falls within "instruction sequence" with some known line
information (see `DWARFDebugLine::LineTable::findRowInSeq()`).

BTF does not provide instruction sequence groupings, thus
`getLineInfoForAddress()` queries only return exact matches.
This does not seem to be a big issue in practice, but output
of the `llvm-objdump -Sd` might differ slightly when BTF
is used instead of DWARF.

[1] https://www.kernel.org/doc/html/latest/bpf/btf.html
[2] https://github.com/libbpf/bpftool

Depends on https://reviews.llvm.org/D149501

Reviewed By: MaskRay, yonghong-song, nickdesaulniers, #debug-info

Differential Revision: https://reviews.llvm.org/D149058
2023-07-12 09:51:09 -07:00
Fangrui Song
bb3e8e90f1 [test] after REQUIRES after D154665
Disassembling needs LLVM_TARGETS_TO_BUILD.
2023-07-12 08:46:05 -07:00