312 Commits

Author SHA1 Message Date
Elvina Yakubova
80a09735ac
Revert "[clang][AArch64] Add getHostCPUFeatures to query for enabled … (#114066)
…features in cpu info (#97749)"

This reverts commit d732c0b13c55259177f2936516b6087d634078e0.

This is breaking buildbots
https://lab.llvm.org/buildbot/#/builders/190/builds/8413,
https://lab.llvm.org/buildbot/#/builders/56/builds/10880 and a few
others.
2024-10-29 14:43:01 +00:00
neildhickey
d732c0b13c
[clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (#97749)
Add getHostCPUFeatures into the AArch64 Target Parser to query the 
cpuinfo for the device in the case where we are compiling with 
-mcpu=native.
Add LLVM_CPUINFO environment variable to test mock /proc/cpuinfo
files for -mcpu=native

Co-authored-by: Elvina Yakubova <eyakubova@nvidia.com>
2024-10-29 13:34:43 +00:00
Freddy Ye
c4248fa3ed
[X86] Support MOVRS and AVX10.2 instructions. (#113274)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-10-25 09:00:19 +08:00
tangaac
5b9c76b6e7
[LoongArch] Support LoongArch-specific amswap[_db].{b/h} and amadd[_db].{b/h} instructions (#113255)
Two options for clang: -mlam-bh & -mno-lam-bh.
Enable or disable amswap[__db].{b/h} and amadd[__db].{b/h} instructions.
The default is -mno-lam-bh.
Only works on LoongArch64.
2024-10-23 16:03:15 +08:00
Carl Ritson
076aac59ac
[AMDGPU] Add a new target for gfx1153 (#113138) 2024-10-23 12:56:58 +09:00
Freddy Ye
9e3d4653af
[X86] Update Model value for Arrow Lake. (#113273)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-10-23 09:44:26 +08:00
hpoussin
c6ba7b38db
[Triple] Make mipsel-*-windows-* use COFF files by default (#107809)
Windows NT/MIPS and Windows CE/MIPS always used COFF format.

This is an extract of PR #107744.
2024-10-15 10:49:17 +08:00
Albert Huang
aa2c0f35a1
[ARM] [AArch32] Add support for Arm China STAR-MC1 CPU (#110085)
STAR-MC1 is an Armv8m CPU.

Technical specifications available at:

https://www.armchina.com/download/Documents/Application-Notes/Technical-Reference-Manual?infoId=160
2024-10-14 15:48:12 +01:00
Michał Górny
387b37af1a
[LLVM] [Clang] Support for Gentoo *t64 triples (64-bit time_t ABIs) (#111302)
Gentoo is planning to introduce a `*t64` suffix for triples that will be
used by 32-bit platforms that use 64-bit `time_t`. Add support for
parsing and accepting these triples, and while at it make clang
automatically enable the necessary glibc feature macros when this suffix
is used.

An open question is whether we can backport this to LLVM 19.x. After
all, adding new triplets to Triple sounds like an ABI change — though I
suppose we can minimize the risk of breaking something if we move new
enum values to the very end.
2024-10-14 11:18:04 +00:00
RipleyTom
c5f7a32356
[X86] Add AMD Llano family detection (#111312)
Very simple one liner, adds the missing detection for the Llano family
which is essentially a refreshed K10:
Documentation of the family id:
https://en.wikichip.org/wiki/amd/cpuid#Family_18_.2812h.29
Documentation that it fits into amdfam10:
https://en.wikipedia.org/wiki/AMD_10h#12h
2024-10-07 08:33:26 -07:00
Yingwei Zheng
bf895c714e
[RISCV] Bump hwprobe support to Linux 6.11 (#108578)
This patch is the follow-up of
https://github.com/llvm/llvm-project/pull/94352 with some updates:
1. Add support for more extensions for `zve*`, `zimop`, `zc*`, `zcmop`
and `zawrs`.
2. Use `RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF` to check whether the
processor supports fast misaligned scalar memory access.
https://github.com/llvm/llvm-project/pull/108551 reminds me that the
patch
https://lore.kernel.org/all/20240809214444.3257596-1-evan@rivosinc.com/T/
has been merged. Address comment
https://github.com/llvm/llvm-project/pull/94352#discussion_r1626056015.

References:
1. constants:
https://github.com/torvalds/linux/blame/v6.11-rc7/arch/riscv/include/uapi/asm/hwprobe.h
2. https://docs.kernel.org/arch/riscv/hwprobe.html
3. Related commits:
1. `zve*` support:
de8f8282a9
2. `zimop` support:
36f8960de8
3. `zc*` support:
0ad70db5eb
4. `zcmop` support:
fc078ea317
5. `zawrs` support:
244c18fbf6
6. scalar misaligned perf:
c42e2f0767
and
1f5288874d
2024-10-05 11:00:09 +08:00
Jonathan Thackray
d0756caedc
[ARM][AArch64] Introduce the Armv9.6-A architecture version (#110825)
This introduces the Armv9.6-A architecture version, including the
relevant command-line option for -march.

More details about the Armv9.6-A architecture version can be found at:
  * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2024
  * https://developer.arm.com/documentation/ddi0602/2024-09/
2024-10-04 10:12:41 +01:00
Piyou Chen
a2994ded60
[RISCV] Fix RISCVBitPositions typo (#110953)
This patch updates  `{"zve64x", 0, 63},` into `{"zve64f", 0, 63},`.

Base on
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions
2024-10-03 14:34:44 +08:00
Jubilee
b8028f6b87
[TargetParser][AArch64] Believe runtime feature detection (#95694)
In https://github.com/llvm/llvm-project/issues/90365 it was reported
that TargetParser arrives at the wrong conclusion regarding what
features are enabled when attempting to detect "native" features on the
Raspberry Pi 4, because it (correctly) detects it as a Cortex-A72, but
LLVM (incorrectly) believes all Cortex-A72s have crypto enabled. Attempt
to help ourselves by allowing runtime information derived from the host
to contradict whatever we believe is "true" about the architecture.
2024-10-02 08:28:57 +01:00
Alex Bradbury
614aeda93b
[RISCV] Mark Zacas as non-experimental (#109651)
The extension has been ratified for some time, but we kept it
experimental (see #99898) due to
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>. The
ABI issue has been resolved by #101023 so I believe there's no known
barrier to moving Zacas to non-experimental.
2024-09-25 06:14:43 +01:00
Alex Rønne Petersen
72a218056d
[llvm][Triple] Add Environment members and parsing for glibc/musl parity. (#107664)
This adds support for:

* `muslabin32` (MIPS N32)
* `muslabi64` (MIPS N64)
* `muslf32` (LoongArch ILP32F/LP64F)
* `muslsf` (LoongArch ILP32S/LP64S)

As we start adding glibc/musl cross-compilation support for these
targets in Zig, it would make our life easier if LLVM recognized these
triples. I'm hoping this'll be uncontroversial since the same has
already been done for `musleabi`, `musleabihf`, and `muslx32`.

I intentionally left out a musl equivalent of `gnuf64` (LoongArch
ILP32D/LP64D); my understanding is that Loongson ultimately settled on
simply `gnu` for this much more common case, so there doesn't *seem* to
be a particularly compelling reason to add a `muslf64` that's basically
deprecated on arrival.

Note: I don't have commit access.
2024-09-20 08:53:03 +08:00
Ganesh
02e4186d0b
[X86] AMD Zen 5 Initial enablement (#107964)
This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.
2024-09-13 17:45:33 +01:00
Kazu Hirata
33e7cd6ff2
[llvm] Prefer StringRef::substr to StringRef::slice (NFC) (#105943)
S.substr(N) is simpler than S.slice(N, StringRef::npos) and
S.slice(N, S.size()). Also, substr is probably better recognizable
than slice thanks to std::string_view::substr.
2024-08-25 11:30:49 -07:00
Craig Topper
371f936c45 [RISCV] Make extension names lower case in RISCVISAInfo::checkDependency() error messages. 2024-08-19 00:22:28 -07:00
Craig Topper
10a4f1ef9e [RISCV] Add helper functions to exploit similarity of some RISCVISAInfo::checkDependency() error strings. NFC 2024-08-19 00:22:28 -07:00
Craig Topper
d489b7ccb7 [RISCV] Merge some ISA error reporting together and make some errors more precise.
Loop over the extension names that have the same error message.

Print the name of Zvk* extensions instead of 'zvk*'.
2024-08-19 00:22:28 -07:00
Pengcheng Wang
a80a90e34b
[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)
These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.
2024-08-19 11:50:32 +08:00
Piyou Chen
82f52d9c42
[RISCV] Support new groupid/bitmask for cpu_model (#101632)
The spec can be found at
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.

1. Add the new extension GroupID/Bitmask with latest hwprobe key.
2. Update the `initRISCVFeature `
3. Update `EmitRISCVCpuSupports` due to not only group0 now.
2024-08-08 14:42:41 +08:00
Aaron Ballman
617cf8a72d
Reapply "Finish deleting the le32/le64 targets" (#99079) (#101983)
This reverts commit d3f8105c65046173e20c4c59394b4a7f1bbe7627.

Halide no longer relies on this target:
https://github.com/llvm/llvm-project/pull/98497#issuecomment-2253358685
2024-08-06 08:35:56 -04:00
Phoebe Wang
259ca9ee9c
Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)" (#101616)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-08-03 09:26:07 +08:00
Phoebe Wang
2e0588d5e1
Revert "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions" (#101612)
Reverts llvm/llvm-project#101452

There are several buildbot failed. Revert first.
2024-08-02 13:04:10 +08:00
Phoebe Wang
10bad2c8d7
[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-08-02 12:10:50 +08:00
Shengchen Kan
95e9afff30 [X86] Update sub-features of APX for host CPU
This is a follow-up for https://github.com/llvm/llvm-project/pull/80636
2024-07-30 18:09:58 +08:00
Chen Zheng
d311edd0ef [PowerPC] fix default cpu setting
for platform that returns nothing for getHostCPUName()
For example for target ARM on windows. For this case, -mcpu=native
should set CPU to the default according to triple instead of setting
CPU to "native"

Fixes https://lab.llvm.org/buildbot/#/builders/161/builds/873 caused by
https://github.com/llvm/llvm-project/pull/97541
2024-07-25 09:55:00 -04:00
Kazu Hirata
74fcb6aafd [TargetParser] Fix warnings
This patch fixes:

  llvm/include/llvm/TargetParser/PPCTargetParser.def:109:9: error:
  suggest braces around initialization of subobject
  [-Werror,-Wmissing-braces]

  llvm/lib/TargetParser/PPCTargetParser.cpp:96:16: error: address of
  stack memory associated with local variable 'CPU' returned
  [-Werror,-Wreturn-stack-address]
2024-07-24 23:57:53 -07:00
Chen Zheng
25482b356e
[PowerPC] add TargetParser for PPC target (#97541)
For now only focus on the CPU type, will work on the CPU features part
later.

With the CPU handling in TargetParser, clang and llc/opt are able to
query common interfaces.

So we can set same default CPU and CPU features with same interfaces.
2024-07-25 13:46:59 +08:00
Aiden Grossman
599f8e1120 Reland "[compiler-rt][X86] Use functions in cpuid.h instead of inline assembly (#97877)"
This reverts commit f1905f064451bf688577976a13000c9c47e58452.

This relands commit 19cf8deabe1124831164987f1b9bf2f806c0a875.

There were issues with the preprocessor includes that should have
excluded MSVC still including clang functions building on windows and
using intrin.h. This relanding fixes this behavior by additionally
wrapping the uses of __get_cpuid and __get_cpuid_count in _MSC_VER so
that clang in MSVC mode, which includes intrin.h, does not have any
conflicts.
2024-07-24 03:58:23 +00:00
Philip Reames
d1e28e2a7b
[RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (#99700)
This implements the __builtin_cpu_init and __builtin_cpu_supports
builtin routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.

This is inspired by https://github.com/llvm/llvm-project/pull/85786.
Major changes are a) a restriction in scope to only the builtins (which
have a much narrower user interface), and the avoidance of false
generality. This change deliberately only handles group 0 extensions
(which happen to be all defined ones today), and avoids the tblgen
changes from that review.

I don't have an environment in which I can actually test this, but @BeMg
has been kind enough to report that this appears to work as expected.

Before this can make it into a release, we need a change such as
https://github.com/llvm/llvm-project/pull/99958. The gcc docs claim that
cpu_support can be called by "normal" code without calling the cpu_init
routine because the init routine will have been called by a high
priority constructor. Our current compiler-rt mechanism does not do
this.
2024-07-23 08:48:28 -07:00
azhan92
1df4d866cc
[PowerPC] Add support for -mcpu=pwr11 / -mtune=pwr11 (#99511)
This PR adds support for -mcpu=pwr11/power11 and -mtune=pwr11/power11 in
clang and llvm.
2024-07-23 09:49:41 -04:00
Ami-zhang
fcec298087
[LoongArch] Support la664 (#100068)
A new ProcessorModel called `la664` is defined in LoongArch.td to
support `-march/-mtune=la664`.
2024-07-23 15:14:20 +08:00
Alex Bradbury
70e7d26e56
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
As discussed at the last sync-up call, mark Zacas as experimental until
this ABI issue is resolved
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>.

Don't return Zacas in getHostCPUFeatures (leaving a TODO there) as even if requesting detection of "native" features, the user likely doesn't want to automatically opt in to experimental codegen.
2024-07-23 08:06:15 +01:00
Ami-zhang
5a1b9896ad
[LoongArch] Support -march=la64v1.0 and -march=la64v1.1 (#100057)
The newly added strings `la64v1.0` and `la64v1.1` in `-march` are as
described in LoongArch toolchains conventions (see [1]).

The target-cpu/feature attributes are forwarded to compiler when
specifying particular `-march` parameter. The default cpu `loongarch64`
is returned when archname is `la64v1.0` or `la64v1.1`.

In addition, this commit adds `la64v1.0`/`la64v1.1` to
"__loongarch_arch" and adds definition for macro "__loongarch_frecipe".

[1]: https://github.com/loongson/la-toolchain-conventions
2024-07-23 14:03:28 +08:00
Daniil Kovalev
146fd7cd45
[PAC][Driver] Support pauthtest ABI for AArch64 Linux triples (#97237)
When `pauthtest` is either passed as environment part of AArch64 Linux
triple
or passed via `-mabi=`, enable the following ptrauth flags:

- `intrinsics`;
- `calls`;
- `returns`;
- `auth-traps`;
- `vtable-pointer-address-discrimination`;
- `vtable-pointer-type-discrimination`;
- `init-fini`.

Some related stuff is still subject to change, and the ABI itself might
be changed, so end users are not expected to use this and the ABI name
has 'test' suffix.

If `-mabi=pauthtest` option is used, it's normalized to effective
triple.

When the environment part of the effective triple is `pauthtest`, try
to use `aarch64-linux-pauthtest` as multilib directory.

The following is not supported:
- combination of `pauthtest` ABI with any branch protection scheme
except BTI;
- explicit set of environment part of the triple to a value different
  from `pauthtest` in combination with `-mabi=pauthtest`;
- usage on non-Linux OS.

---------

Co-authored-by: Anatoly Trosinenko <atrosinenko@accesssoftek.com>
2024-07-22 21:18:39 +03:00
Jie Fu
8dafbb5fdd [RISCV] Remove unused function (NFC)
/llvm-project/llvm/lib/TargetParser/RISCVTargetParser.cpp:148:1:
error: unused function 'getExtensionBitmask' [-Werror,-Wunused-function]
getExtensionBitmask(StringRef ExtName) {
^
1 error generated.
2024-07-22 14:33:45 +08:00
Piyou Chen
f4d4ce1a31
[RISCV] Add groupid/bitmask for RISC-V extension (#94440)
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.

This patch defines the groupid/bitmask in RISCVFeatures.td and generates
the corresponding table in RISCVTargetParserDef.inc.

The groupid/bitmask of extensions provides an abstraction layer between
the compiler and runtime functions.
2024-07-22 14:18:05 +08:00
James Y Knight
3c6ea7b716
Remove 3DNow! from X86TargetParser. (#99352)
This addresses the spurious inclusion of (now unsupported) target
features '-3dnow' and '-3dnowa' when disabling mmx (when then caused log
output from `clang -mno-mmx`).

It should've been part of PR #96246, but was missed.

Also tweaks the warning in prfchwintrin.h to not recommend the
deprecated mm3dnow.h header.
2024-07-20 11:28:06 -04:00
Aaron Ballman
d3f8105c65
Revert "Finish deleting the le32/le64 targets" (#99079)
Reverts llvm/llvm-project#98497

We're reverting this for approx 30 days so that the Halide project has
time to transition off the target.
2024-07-16 14:47:09 -04:00
Yingwei Zheng
578cf724de
[RISCV] Add support for getHostCPUFeatures using hwprobe (#94352)
This patch adds support for `sys::getHostCPUFeatures` using the RISC-V
hardware probing interface.
References:
+ Loongarch patch:
e53f41c39f
+ asm/hwprobe.h:
2ab7951410/arch/riscv/include/uapi/asm/hwprobe.h
+ glibc support:
https://inbox.sourceware.org/glibc-cvs/20240301151728.AD5963858C53@sourceware.org/T/#Z2e.:..:20240301151728.AD5963858C53::40sourceware.org:1sysdeps:unix:sysv:linux:riscv:sys:hwprobe.h
+ __NR_riscv_hwprobe syscall tutorial:
https://github.com/cyyself/hwprobe
+ hwprobe docs: https://docs.kernel.org/arch/riscv/hwprobe.html

---------

Co-authored-by: Yangyu Chen <cyy@cyyself.name>
2024-07-16 10:11:39 +08:00
Craig Topper
73acf8d755
[RISCV] Add -m[no-]scalar-strict-align and -m[no-]vector-strict-align. (#95024) 2024-07-14 13:39:17 -07:00
Aaron Ballman
2369a54fbe
Finish deleting the le32/le64 targets (#98497)
This is a revert of ef5e7f90ea4d5063ce68b952c5de473e610afc02 which was a
temporary partial revert of 77ac823fd285973cfb3517932c09d82e6a32f46d.
The le32 and le64 targets are no longer necessary to retain, so this
removes them entirely.
2024-07-12 06:55:49 -04:00
David Spickett
18e70a4d50
[llvm][TargetParser] Return StringMap from getHostCPUFeatures (#97824)
Previously this took a reference to a map and returned a bool to say
whether it succeeded. We can return a StringMap instead, as all callers
but 1 simply iterated the map if the bool was true, and passed in empty
maps as the starting point.

lldb's lit-cpuid did specifically check whether the call failed, but due
to the way the x86 routines work this works out the same as checking if
the returned map is empty.
2024-07-11 10:32:43 +01:00
Shao-Ce SUN
cd6750fa5f
[RISCV][NFC] Add a newline when using --print-enabled-extensions (#98425)
The `--print-enabled-extensions` has been introduced in the
https://github.com/llvm/llvm-project/pull/98207 , but it seems to be
missing a newline in the end.
2024-07-11 12:43:14 +08:00
R
3c5f929ad0
[RISCV] Add QingKe "XW" compressed opcode extension (#97925)
This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.

These opcodes are found in some RISC-V microcontrollers from WCH /
Nanjing Qinheng Microelectronics.

As discussed in the Discourse forums, this uses incompatible extension
and opcode names vs the vendor binary toolchain. The chosen names
instead follow the conventions for other vendor extensions listed on the
"riscv-non-isa" project.
2024-07-11 11:10:02 +08:00
Michael Maitland
eee5d2d37c
[RISCV] Add ability to list extensions enabled for a target (#98207)
bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option. This patch
adds documentation for this option.

`riscvExtensionsHelp` is renamed to `printSupportedExtensions` to by
synonymous with AArch64 and so it is clear what that function does.
2024-07-10 15:39:08 -04:00
Craig Topper
66470112d6
[RISCV] Don't expose any constructors of RISCVISAInfo publicly. (#98249)
lld was using RISCVISAInfo(unsigned XLen,
RISCVISAUtils::OrderedExtensionMap &Exts). This required a call to
RISCVISAInfo::postProcessAndChecking to validate the RISCVISAInfo that
was created. This exposes too much about RISCVISAInfo to lld.

Replace with a new RISCVISAInfo::createFromExtMap that is responsible
for creating the object and calling postProcessAndChecking.
2024-07-09 19:35:25 -07:00