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Author SHA1 Message Date
Matt Arsenault
fc3e6a8186
DAG: Handle lowering unordered compare with inf (#100378) 
Try to take advantage of the nan check behavior of fcmp.
x86_64 looks better, x86_32 looks worse.
 2024-09-05 19:54:32 +04:00
Yingwei Zheng
38a44bdc93
[CodeGenPrepare] Reverse the canonicalization of isInf/isNanOrInf (#81572) 
In commit
2b582440c1,
we canonicalize the isInf/isNanOrInf idiom into fabs+fcmp for better
analysis/codegen (See also the discussion in
https://github.com/llvm/llvm-project/pull/76338).

This patch reverses the fabs+fcmp to `is.fpclass`. If the `is.fpclass`
is not supported by the target, it will be expanded by TLI.

Fixes the regression introduced by
2b582440c1
and
https://github.com/llvm/llvm-project/pull/80414#issuecomment-1936374206.
 2024-03-18 18:27:45 +08:00
Qiu Chaofan
b46e768455
[DAGCombine] Fold setcc_eq infinity into is.fpclass (#67829) 2023-11-01 11:51:15 +09:00
Qiu Chaofan
cc627828f5 Pre-commit some PowerPC test cases 2023-09-28 15:51:14 +08:00
Qiu Chaofan
b922a36211 [PowerPC] Define SchedModel for Power8 
PowerPC subtargets prior to Power9 use the 'legacy' itinerary way to
provide scheduling information. This patch re-writes the tablegen file
to define the scheduling information in the new SchedModel way, which
can bring improvements to some benchmarks.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D154488
 2023-09-08 15:43:21 +08:00
Ting Wang
52a774fd4c [PowerPC] remove XXSWAPD after load from CP which is a splat value 
If the value from constant-pool is a splat value of vector type, do not
need swap after load from constant-pool.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D139491
 2023-02-16 19:21:35 -05:00
Qiu Chaofan
b9be5a6823 Pre-commit PowerPC case for zero/inf fpclassify 2022-11-25 17:37:41 +08:00