16 Commits

Author SHA1 Message Date
Benjamin Kramer
b44470547e Make helpers static. NFC. 2020-07-09 13:48:56 +02:00
George Mitenkov
7a4e39b326 [MLIR][SPIRVToLLVM] Implementation of spv.BitFieldSExtract and spv.BitFieldUExtract patterns
This patch adds conversion patterns for `spv.BitFieldSExtract` and `spv.BitFieldUExtract`.
As in the patch for `spv.BitFieldInsert`, `offset` and `count` have to be broadcasted in
vector case and casted to match the type of the base.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D82640
2020-07-08 12:37:37 +03:00
George Mitenkov
00580349c3 [MLIR][SPIRVToLLVM] Miscellaneous ops conversion: select, fmul and undef
This patch introduces 3 new direct conversions for SPIR-V ops:
- `spv.Select`
- `spv.Undef`
- `spv.FMul` that was skipped in the patch with arithmetic ops

Differential Revision: https://reviews.llvm.org/D83291
2020-07-08 11:06:04 +03:00
George Mitenkov
1cfaaf6455 [MLIR][SPIRVToLLVM] Convert spv.constant scalars and vectors
This patch introduces conversion pattern for `spv.constant` with scalar
and vector types. There is a special case when the constant value is a
signed/unsigned integer (vector of integers). Since LLVM dialect does not
have signedness semantics, the types had to be converted to signless ints.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D82936
2020-07-02 14:26:58 -04:00
George Mitenkov
8119a374bc [MLIR][SPIRVToLLVM] SPIR-V function call conversion pattern
Added conversion pattern for SPIR-V `FunctionCallOp`. Based on
specification, it returns no results or a single result, so
can be mapped directly to LLVM dialect's `llvm.call`.

Reviewed By: antiagainst, ftynse

Differential Revision: https://reviews.llvm.org/D83030
2020-07-02 12:38:27 -04:00
George Mitenkov
03fe7eb16f [MLIR][SPIRVToLLVM] Implementation of spv.BitFieldInsert pattern
This patch introduces conversion pattern for `spv.BitFiledInsert` op,
as well as some utility functions to facilitate code reading.
Since `spv.BitFiledInsert` may take both vector and integer operands,
this case was specifically handled by broadcasting values (`count`
and `offset` here) to vectors. Moreover, the types had to be converted
to same bitwidth in order to conform with LLVM dialect rules.
This was done with `zext` when extending (Note that `count` and
`offset` are treated as unsigned) and `trunc` in the opposite case.
For the latter one, truncation is safe since the op is defined only when
`count`/`offset`/their sum is less than the bitwidth of the result.
This introduces a natural bound of the value of 64, which can be
expressed as `i8`.

Reviewed By: antiagainst, ftynse

Differential Revision: https://reviews.llvm.org/D82639
2020-07-02 12:19:12 -04:00
George Mitenkov
3819789be6 [MLIR][SPIRVToLLVM] Added Bitcast conversion pattern
Added conversion pattern and tests for `spv.Bitcast` op.  This one has
a direct mapping in LLVM dialect so `DirectConversionPattern` was used.

Differential Revision: https://reviews.llvm.org/D82748
2020-06-29 20:32:48 -04:00
George Mitenkov
cd1bc5c15d [MLIR][SPIRVToLLVM] Convert bitwise and logical not
This patch introduces new conversion patterns for bit and logical
negation op: `spv.Not` and `spv.LogicalNot`. They are implemented
by applying xor on the operand and mask with all bits set.

Differential Revision: https://reviews.llvm.org/D82637
2020-06-29 19:16:50 -04:00
George Mitenkov
c8295de4a6 [MLIR][SPIRVToLLVM] Conversion for bitrverse and bitcount ops
Implemented conversion for `spv.BitReverse` and `spv.BitCount`. Since ODS
generates builders in a different way for LLVM dialect intrinsics, I
added attributes to build method in `DirectConversionPattern` class. The
tests for these ops are in `bitwise-ops-to-llvm.mlir`.

Differential Revision: https://reviews.llvm.org/D82286
2020-06-26 10:30:52 -04:00
George Mitenkov
b5c24c24a4 [MLIR][SPIRVToLLVM] Implementation of SPIR-V module conversion pattern
This patch introduces conversion patterns for `spv.module` and `spv._module_end`.
SPIR-V module is converted into `ModuleOp`. This will play a role of enclosing
scope to LLVM ops. At the moment, SPIR-V module attributes (such as memory model,
etc) are ignored.

Differential Revision: https://reviews.llvm.org/D82468
2020-06-24 20:42:50 -04:00
George Mitenkov
a4dc61344f [MLIR][SPIRVToLLVM] Implementation of spv.func conversion, and return ops
This patch provides an implementation for `spv.func` conversion. The pattern
is populated in a separate method added to the pass. At the moment, the type
signature conversion only includes the supported types. The conversion pattern
also matches SPIR-V function control attributes to LLVM function attributes.
Those are modelled as `passthrough` attributes in LLVM dialect. The following
mapping are used:
- None: no attributes passed
- Inline: `alwaysinline` seems to be the right equivalent (`inlinehint` is
  semantically weaker in my opinion)
- DontInline: `noinline`
- Pure and Const: I think those can be modelled as `readonly` and `readnone`
  attributes respectively.

Also, 2 patterns added for return ops conversion (`spv.Return` for void return
and `spv.ReturnValue` for a single value return).

Differential Revision: https://reviews.llvm.org/D81931
2020-06-23 11:34:11 -04:00
George Mitenkov
771b788687 [MLIR][SPIRVToLLVM] Support cast ops, some logical ops, UModOp
Added support of simple logical ops: `LogicalAnd`, `LogicalOr`,
`LogicalEqual` and `LogicalNotEqual`. Added a missing conversion
for `UMod` op.

Also, implemented SPIR-V cast ops conversion. There are 4 simple
case where there is a clear equivalent in LLVM (e.g. `ConvertFToS`
is `fptosi`). For `FConvert`, `SConvert` and `UConvert` we
distinguish between truncation and extension based on the bit
width of the operand.

Differential Revision: https://reviews.llvm.org/D81812
2020-06-17 17:46:45 -04:00
George Mitenkov
cf2b4d5cb6 [MLIR][SPIRVToLLVM] Implemented shift conversion pattern
This patch has shift ops conversion implementation. In SPIR-V dialect,
`Shift` and `Base` may have different bit width. On the contrary,
in LLVM dialect both `Base` and `Shift` have to be of the same bit width.
This leads to the following cases:
- if `Base` has the same bit width as `Shift`, the conversion is
  straightforward.
- if `Base` has a greater bit width than `Shift`, shift is sign/zero
  extended first. Then the extended value is passed to the shift.
- otherwise the conversion is considered to be illegal.

Differential Revision: https://reviews.llvm.org/D81546
2020-06-12 19:04:30 -04:00
George Mitenkov
fc148a4c88 [MLIR][SPIRVToLLVM] Added conversion for SPIR-V comparison ops
Implemented `FComparePattern` and `IComparePattern` classes
that provide conversion of SPIR-V comparison ops (such as
`spv.FOrdGreaterThanEqual` and others) to LLVM dialect.
Also added tests in `comparison-ops-to-llvm.mlir`.

Differential Revision: https://reviews.llvm.org/D81487
2020-06-11 18:46:17 -04:00
George Mitenkov
d93d8fcdec [MLIR][SPIRVToLLVM] Implemented conversion for arithmetic ops and 3 bitwise ops.
Following the previous revision `D81100`, this commit implements a templated class
that would provide conversion patterns for “straightforward” SPIR-V ops into
LLVM dialect. Templating allows to abstract away from concrete implementation
for each specific op. Those are mainly binary operations. Currently supported
and tested ops are:
- Arithmetic ops: `IAdd`, `ISub`, `IMul`, `FAdd`, `FSub`, `FMul`, `FDiv`,  `FNegate`,
  `SDiv`, `SRem` and  `UDiv`
- Bitwise ops: `BitwiseAnd`, `BitwiseOr`, `BitwiseXor`

The implementation relies on `SPIRVToLLVMConversion` class that makes use of
`OpConversionPattern`.

Differential Revision: https://reviews.llvm.org/D81305
2020-06-10 19:10:31 -04:00
George Mitenkov
fda5192d4f [MLIR][SPIRVToLLVM] Add skeleton for SPIR-V to LLVM dialect conversion
These commits set up the skeleton for SPIR-V to LLVM dialect conversion.
I created SPIR-V to LLVM pass, registered it in Passes.td, InitAllPasses.h.
Added a pattern for `spv.BitwiseAndOp` and tests for it. Integer, float
and vector types are converted through LLVMTypeConverter.

Differential Revision: https://reviews.llvm.org/D81100
2020-06-08 18:22:42 -04:00