261 Commits

Author SHA1 Message Date
Chad Rosier
aaa55a88b6 [fast-isel] Add support for UDIV.
llvm-svn: 149712
2012-02-03 21:07:27 +00:00
Chad Rosier
41f0e78b6c [fast-isel] Add support for FPToUI. Also add test cases for FPToSI.
llvm-svn: 149706
2012-02-03 20:27:51 +00:00
Chad Rosier
a8a8ac5d47 [fast-isel] Add support for selecting UIToFP.
llvm-svn: 149704
2012-02-03 19:42:52 +00:00
David Blaikie
46a9f016c5 More dead code removal (using -Wunreachable-code)
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Eric Christopher
d284c1d80d Fix assert.
llvm-svn: 147966
2012-01-11 20:55:27 +00:00
Jakob Stoklund Olesen
083dbdca7f Match SelectionDAG logic for enabling movt.
Darwin doesn't do static, and ELF targets only support static.

llvm-svn: 147740
2012-01-07 20:49:15 +00:00
Jakob Stoklund Olesen
8cdce7e690 Use getRegForValue() to materialize the address of ARM globals.
This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.

<rdar://problem/10658692>

llvm-svn: 147720
2012-01-07 04:07:22 +00:00
Jakob Stoklund Olesen
68f034ee1a Use movw+movt in ARMFastISel::ARMMaterializeGV.
This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.

This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.

<rdar://problem/10629774>

llvm-svn: 147712
2012-01-07 01:47:05 +00:00
Evan Cheng
68132d8093 ARM target code clean up. Check for iOS, not Darwin where it makes sense.
llvm-svn: 146981
2011-12-20 18:26:50 +00:00
Chad Rosier
ded6160473 VFP2 is required for FP loads. Noticed by inspection.
llvm-svn: 146569
2011-12-14 17:55:03 +00:00
Chad Rosier
fce28914ea Tidy up.
llvm-svn: 146568
2011-12-14 17:32:02 +00:00
Chad Rosier
a26979be29 Fix 80-column violation and extraneous brackets.
llvm-svn: 146566
2011-12-14 17:26:05 +00:00
Evan Cheng
7fae11b231 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
2011-12-14 02:11:42 +00:00
Chad Rosier
563de603f7 [fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
load and then move the result from a GPR to a FPR.

llvm-svn: 146502
2011-12-13 19:22:14 +00:00
Evan Cheng
7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Chad Rosier
c77830d21e [arm-fast-isel] Doublewords only require word-alignment.
rdar://10528060

llvm-svn: 145891
2011-12-06 01:44:17 +00:00
Bob Wilson
80381f6cbf Fix 80-column issues.
llvm-svn: 145783
2011-12-04 00:52:23 +00:00
Chad Rosier
ec3b77e00d [arm-fast-isel] Unaligned stores of floats require special care.
rdar://10510150

llvm-svn: 145742
2011-12-03 02:21:57 +00:00
Nick Lewycky
50f02cb21b Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
2011-12-02 22:16:29 +00:00
Chad Rosier
9fd0e55e91 [arm-fast-isel] After promoting a function parameter be sure to update the
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

llvm-svn: 145701
2011-12-02 20:25:18 +00:00
Duncan Sands
12330650f8 Silence wrong warnings from GCC about variables possibly being used
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.

llvm-svn: 145239
2011-11-28 10:31:27 +00:00
Chad Rosier
ee93ff736a Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
llvm-svn: 144959
2011-11-18 01:17:34 +00:00
Chad Rosier
0eff3e5c21 Add TODO comment.
llvm-svn: 144920
2011-11-17 21:46:13 +00:00
Chad Rosier
15b2498e88 Dead code.
llvm-svn: 144888
2011-11-17 07:24:49 +00:00
Chad Rosier
ce619ddfc5 Don't unconditionally set the kill flag.
rdar://10456186

llvm-svn: 144872
2011-11-17 01:16:53 +00:00
Chad Rosier
80979b6ea6 Check to make sure we can select the instruction before trying to put the
operands into a register.  Otherwise, we may materialize dead code.

llvm-svn: 144805
2011-11-16 18:39:44 +00:00
Chad Rosier
af13d767a2 Add FIXME comment.
llvm-svn: 144743
2011-11-16 00:32:20 +00:00
Jay Foad
0745e645e0 Remove some unnecessary includes of PseudoSourceValue.h.
llvm-svn: 144631
2011-11-15 07:24:32 +00:00
Chad Rosier
057b6d3476 Supporting inline memmove isn't going to be worthwhile. The only way to avoid
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.

llvm-svn: 144585
2011-11-14 23:04:09 +00:00
Chad Rosier
ab7223e99a Add support for inlining small memcpys.
rdar://10412592

llvm-svn: 144578
2011-11-14 22:46:17 +00:00
Chad Rosier
45110fdf8d Fix a performance regression from r144565. Positive offsets were being lowered
into registers, rather then encoded directly in the load/store.

llvm-svn: 144576
2011-11-14 22:34:48 +00:00
Chad Rosier
adfd200bcb Add support for Thumb load/stores with negative offsets.
rdar://10412592

llvm-svn: 144565
2011-11-14 20:22:27 +00:00
Chad Rosier
2a1df883d0 Add support for ARM halfword load/stores and signed byte loads with negative
offsets.
rdar://10412592

llvm-svn: 144518
2011-11-14 04:09:28 +00:00
Chad Rosier
1198d894d0 The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
llvm-svn: 144494
2011-11-13 09:44:21 +00:00
Chad Rosier
a476e391f1 Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
llvm-svn: 144492
2011-11-13 05:14:43 +00:00
Chad Rosier
5196efdf36 Fix comments.
llvm-svn: 144490
2011-11-13 04:25:02 +00:00
Chad Rosier
c8cfd3a8fb Add support for emitting both signed- and zero-extend loads. Fix
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1

llvm-svn: 144488
2011-11-13 02:23:59 +00:00
Chad Rosier
a7ebc5617d Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
llvm-svn: 144426
2011-11-11 23:31:03 +00:00
Chad Rosier
e19b0a9eb8 Rename variables to avoid confusion. No functionallity change intended.
llvm-svn: 144377
2011-11-11 06:27:41 +00:00
Chad Rosier
7ddd63ce4e Add support for using immediates with select instructions.
rdar://10412592

llvm-svn: 144376
2011-11-11 06:20:39 +00:00
Chad Rosier
023ede5649 When loading a value, treat an i1 as an i8.
llvm-svn: 144356
2011-11-11 02:38:59 +00:00
Chad Rosier
2a3503e061 Add support for using MVN to materialize negative constants.
rdar://10412592

llvm-svn: 144348
2011-11-11 00:36:21 +00:00
Chad Rosier
d1762e00e2 When in ARM mode, LDRH/STRH require special handling of negative offsets.
For correctness, disable this for now.
rdar://10418009

llvm-svn: 144316
2011-11-10 21:09:49 +00:00
Chad Rosier
3fbd094ad9 For immediate encodings of icmp, zero or sign extend first. Then
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
2011-11-10 01:30:39 +00:00
Chad Rosier
2f27fab6ed The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
rdar://10418009

llvm-svn: 144213
2011-11-09 21:30:12 +00:00
Chad Rosier
595d419427 Add support for encoding immediates in icmp and fcmp. Hopefully, this will
remove a fair number of unnecessary materialized constants.
rdar://10412592

llvm-svn: 144163
2011-11-09 03:22:02 +00:00
Chad Rosier
0439cfc41f ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
No functional change intended.

llvm-svn: 144122
2011-11-08 21:12:00 +00:00
Chad Rosier
5de1bea5c9 Enable support for returning i1, i8, and i16. Nothing special todo as it's the
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047
2011-11-08 00:03:32 +00:00
Chad Rosier
d0191a53c9 Add support for passing i1, i8, and i16 call parameters. Also, be sure to
zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.

llvm-svn: 143821
2011-11-05 20:16:15 +00:00
Chad Rosier
5b8fdd7b62 Cannot create a result register for non-legal types.
llvm-svn: 143749
2011-11-04 23:45:39 +00:00