2 Commits

Author	SHA1	Message	Date
sstwcw	2e32ff106e	[clang-format] Handle Verilog preprocessor directives ... Verilog uses the backtick instead of the hash. In this revision backticks are lexed manually and then get labeled as hashes so the logic for handling C preprocessor stuff don't have to change. Hashes get labeled as identifiers for Verilog-specific stuff like delays. Reviewed By: HazardyKnusperkeks Differential Revision: https://reviews.llvm.org/D124749	2022-06-26 02:02:29 +00:00
sstwcw	9ed2e68c9a	[clang-format] Parse Verilog if statements ... This patch mainly handles treating `begin` as block openers. While and for statements will be handled in another patch. Reviewed By: HazardyKnusperkeks Differential Revision: https://reviews.llvm.org/D123450	2022-06-26 01:52:15 +00:00