12 Commits

Author SHA1 Message Date
Matthias Springer
ae9e1d1df4 [mlir][SparseTensor] Fix incorrect API usage in RewritePatterns
Incorrect API usage was detected by D144552.

Differential Revision: https://reviews.llvm.org/D145166
2023-03-02 17:59:57 +01:00
wren romano
9916ab03f1 [mlir][sparse] (re)introducing getRankedTensorType/getMemrefType
The bulk of D142074 seems to have gotten overwritten due to some sort of merge conflict (afaict there's no record of it having been reverted intentionally).  So this commit redoes those changes.  In addition to the original changes, this commit also:
* moves the definition of `getRankedTensorType` (from `Transforms/CodegenUtils.h` to `IR/SparseTensor.h`), so that it can be used by `IR/SparseTensorDialect.cpp`.
* adds `getMemRefType` as another abbreviation.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D142503
2023-01-25 11:29:54 -08:00
Aart Bik
3ab0067278 [mlir][sparse] layout fixes (NFC)
Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D140761
2022-12-29 12:30:02 -08:00
Peiming Liu
781eabeb40 [mlir][sparse] refactoring loop emitter into its own files.
Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D140701
2022-12-27 19:12:05 +00:00
Aart Bik
431f6a543e [sparse][mlir][vectorization] add support for shift-by-invariant
Reviewed By: Peiming

Differential Revision: https://reviews.llvm.org/D140596
2022-12-27 11:07:13 -08:00
Mehdi Amini
9f7de08ba6 Apply clang-tidy fixes for llvm-else-after-return in SparseVectorization.cpp (NFC) 2022-12-22 15:33:01 +00:00
Aart Bik
70ac598197 [mlir][sparse][simd] only accept proper unit stride subscripts
Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D139983
2022-12-14 13:07:14 -08:00
Aart Bik
16aa4e4bd1 [mlir][sparse] introduce sparse vectorization to the sparse compiler pipeline
Reviewed By: Peiming

Differential Revision: https://reviews.llvm.org/D139581
2022-12-07 16:06:53 -08:00
Adrian Kuegel
f083c9bdef [mlir][SparseTensor] Apply ClangTidyLegacy finding (NFC).
Converting integer literal to bool, use bool literal instead.
2022-12-06 13:29:47 +01:00
Aart Bik
2fda620711 [mlir][sparse][vectorization] implement "index" vectorization
This adds the capability to vectorize computations like a[i] = i.
This also generalizes the supported unary and binary ops and
adds a test for each to ensure actual SIMD code can result.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D138956
2022-11-30 11:40:05 -08:00
Aart Bik
cb82d375a8 [mlir][sparse][vectorization] optimize reduction chains
A few more dots on the i's of the sparse vectorizer.
Also makes reduction matching less brittle.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D138513
2022-11-26 12:40:51 -08:00
Aart Bik
99b3849d89 [mlir][sparse] introduce vectorization pass for sparse loops
This brings back previous SIMD functionality, but in a separate pass.
The idea is to improve this new pass incrementally, going beyond for-loops
to while-loops for co-iteration as welll (masking), while introducing new
abstractions to make the lowering more progressive. The separation of
sparsification and vectorization is a very good first step on this journey.

Also brings back ArmSVE support

Still to be fine-tuned:
  + use of "index" in SIMD loop (viz. a[i] = i)
  + check that all ops really have SIMD support
  + check all forms of reductions
  + chain reduction SIMD values

Reviewed By: dcaballe

Differential Revision: https://reviews.llvm.org/D138236
2022-11-21 16:12:12 -08:00