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6 Commits

Author SHA1 Message Date
Tim Northover
cbcb7a37f7 AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed 
Sometimes we need emit the bits that would actually be a MOVN when producing a
relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got
wrong until now.

llvm-svn: 206289
 2014-04-15 14:00:15 +00:00
Bradley Smith
5511f08055 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value. 
llvm-svn: 205883
 2014-04-09 14:43:40 +00:00
Bradley Smith
8f906a3c5f [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. 
llvm-svn: 205877
 2014-04-09 14:43:15 +00:00
Bradley Smith
bc35b1f138 [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 
llvm-svn: 205874
 2014-04-09 14:43:01 +00:00
Bradley Smith
2ba17a4a17 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent. 
llvm-svn: 205867
 2014-04-09 14:42:27 +00:00
Tim Northover
00ed9964c6 ARM64: initial backend import 
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

llvm-svn: 205090
 2014-03-29 10:18:08 +00:00